Your method of placing a small 3.3V island under the FPGA is probably
required because of the large number of pins that need to connect to the
3.3V. When you do this, allow for plenty of bypassing to ground on the 3.3V
plane near and under the part. Also you may want to consider stitching the
3.3V plane to the VCC plane with high frequency caps (.1 and .01ufd) to
provide a signal return for the signals that cross from one reference one
voltage plane to another.
Bob Davis, Consulting Engineer
Summit Computer Systems, Inc
Signal Integrity Specialists - High Speed, Critical PCB Design
firstname.lastname@example.org , www.scsi.com
[mailto:owner-si-list@silab.Eng.Sun.COM] On Behalf Of Poulet P.
Sent: Friday, November 06, 1998 10:01 AM
Subject: [SI-LIST] : 5v and 3.3v
I will have on the new design I am working on a single component (FPGA)
at VCC3.3V. The rest of the board is 5V. Board size is "small" 3"x5",
frequencies are under 40Mhz although rise time may be a problem. The
amount of current on the 3.3v is estimated under 200mA so we plan to use
a simple reg to generate 3.3v for 5V. We project 6 layers including Gnd
and VCC5v plane. How would be the more efficient way to route the 3.3V.
We obviously don't want to have a specific 3.3v plane just for 1
I plan to build under the FPGA a small 3.3V plane placed inside the 5V
Any input on this subject greatly appreciated.
3001 Orchard Pkwy
San Jose CA95134-2088
**** To unsubscribe from si-list: send e-mail to
email@example.com. In the BODY of message put: UNSUBSCRIBE
si-list, for more help, put HELP. si-list archives are accessible at
**** To unsubscribe from si-list: send e-mail to firstname.lastname@example.org. In the BODY of message put: UNSUBSCRIBE si-list, for more help, put HELP. si-list archives are accessible at http://www.qsl.net/wb6tpu/si-list ****