Re: Simultaneous Switching and differential buffer skew

Joe Cahill ([email protected])
Mon, 14 Jul 1997 12:23:01 -0400

Something has to be driving your differential buffers, check these for
simultaneous switch effects.
Check the buffer designs, there may be hidden current spikes. Theoretically the
current should be constant in a current switch, but in practice it is possible
to create a design with current spikes.
Perhaps this is obvious, and you have already thought of it, but check your
card wiring to be sure it is truly differential.
Check the common mode return path. Even good differential wiring on cards
involves a common mode return path. If that is poor you could introduce
differential noise.


alaa @
07/14/97 05:21 AM
Please respond to [email protected] @ internet

To: si-list @ silab.Eng.Sun.COM @ internet
cc: alaa @ @ internet
Subject: Simultaneous Switching

Hi SI Colleagues,

The issue of simultaneous switching is very important in normal CMOS buffers due
to the high dI/dt generated which may cause considerable ground bounce/power
droop. In the case of differential buffers that use current steering design, the
dI/dt is usually small and diminishes in a very short time yet when we switch a
large number of differential buffers simultaneously we can notice some pulse
width jitter in the transmitted signal. This is in the form of varying delay
which can impact the setup and hold time particularly at high frequency (>250

Now the question is do you think simultaneous switching is an issue in
differential buffers which use current steering design? and if yes, has anyone
done some analysis on the effect of SSO on pulse width jitter?

All feedback are welcome.


Dr. Alaa F. Alani
Senior Signal Integrity Eng. Tel: +44 (0)1344-413383
LSI-Logic Europe Ltd. Fax: +44 (0)1344-413186
Greenwood House, London Road
Bracknell, Berks RG12 2UB E-Mail: [email protected]