Some of us out here really do methodically design decoupling caps into
the product. The methodology was developed and published by:
Larry D Smith,
Decoupling Capacitor Calculations for CMOS Circuits,
Electrical Performance of Electrical Packages Conference,
Monterey CA, Nov 1994,
Since the methodology was published, it has been used it on several
products. Lab measurements with a spectrum analyzer indicate greatly
reduced power supply noise at many frequencies. Also, EMC/EMI radiation
has been measured as much as 10 dB down after using the methodology.
BTW, that guy from IBM works for Sun now... :)
Larry D Smith
> From firstname.lastname@example.org Mon Apr 28 11:06:16 1997
> Date: Mon, 28 Apr 1997 12:05:12 -0600
> From: email@example.com (Gary Peterson)
> To: firstname.lastname@example.org
> Subject: Re: Power/ground connections/bypassing on ICs
> I can't remain quiet on this issue any longer.
> We all know about minimizing and reducing, etc. But does anyone out there
> actually DESIGN their bypassing networks? I sure don't know how to do it!
> If I did, perhaps I could design a bypass network that would serve my needs
> AND the needs of the assembly/manufacturing folks. A few years back, at a
> SPICE class in San Jose, I heard a fellow from IBM state that he designed his
> bypassing networks in the frequency domain. Anyone else doing this?
> I've tried, but without satisfactory results. Any suggestions on scaling
> the problem? Any ideas on how to model the timing jitter between parts
> that are simultaneously switching with ~2ns edges? Are there any bypass network
> designers out there? I'm sure I (at least) could use some real design help on
> this one. No opinions, intuitions or hand-waving please. I have plenty of my
> own and they are probably more conservative than need be.
> Gary P.