[SI-LIST] : EPEP'97 ADVANCED PROGRAM

Alina Deutsch (DEUTSCH@watson.ibm.com)
Mon, 08 Sep 1997 10:33:37 -0700

EPEP'97 ADVANCED PROGRAM

6th Topical Meeting on Electrical Performance of Electronic Packaging

EPEP '97

Sponsored by

The IEEE Microwave Theory and Techniques Society

and

The IEEE Components, Packaging and Manufacturing Technology Society

October 27 - 29, 1997
The Wyndham Hotel
San Jose, California

INTRODUCTION

The 6th Topical Meeting on Electrical Performance of Electronic
Packaging
provides a forum for the presentation and discussion of the latest
advances in electrical design, analysis and characterization of on-chip
and packaging interconnections and structures for digital, mixed signal,
RF, microwave and mm-Wave applications.

The meeting is aimed at bringing together researchers and practicing
engineers from industries, universities and government laboratories from
around the world to address all current and future issues affecting the
electrical performance of high-speed electronic systems. The conference
is organized into thirteen oral sessions and one open forum (poster) for
one-on-one discussions.

Two important topics are being highlighted this year through two
dedicated
sessions for each. These are the need for developing fast and accurate
full-chip wiring parameter extraction tools and the need for new
developments in the modeling and simulation techniques that can handle
increasingly larger portions of the system packaging. Both topics are
generated by the shifting boundaries of the various chip and package
integration levels and higher performance requirements. Six invited
talks
address important topics such as cost-performance, and power
distribution
considerations in medium and high-performance servers and workstations;
on-chip interconnect modeling; efficiency improvements in modeling and
simulation tools.

Informal interactions are greatly encouraged during the time available
between sessions and at the evening open forum and museum excursion.
Five
short courses are also offered the day before the start of the meeting.
The tutorials are given by well-known experts in the field and cover
important aspects of electrical packaging design, modeling, and
characterization.

The Meeting Chairs thank the authors, presenters, instructors and
technical program committee members for their contributions in putting
together such an outstanding technical program. The sponsorship of the
IEEE Microwave Theory and Techniques Society and the IEEE Components,
Packaging, and Manufacturing Technology Society is acknowledged, and the
individual company sponsorships are greatly appreciated.

Alina Deutsch
Vijai K. Tripathi

Meeting Co-Chairs

Technical Program Committee

T. Arabi, Intel Corporation
A. Cangellaris, University of Illinois
A. Deutsch, IBM Corporation
D. DeGroot, NIST
P. Franzon, North Carolina State University
T. Itoh, UCLA
L. Katehi, University of Michigan
G. Katopis, IBM Corporation
R. Kaw, Hewlett-Packard
R. Kemerley, US Air Force
K. Lee, Hewlett-Packard
L. Martens, University of Gent
C. Park, Kyocera America, Inc.
J. Prince, University of Arizona
H. Reichl, Technical University of Berlin
K. Roselle, Cadence Design Systems Inc.
M. Swaminathan, Georgia Institute of Technology
V. Tripathi, Oregon State University
K. Utsumi, NEC Corporation

International Advisory Committee

E. Davidson, IBM Corporation
D. DeZutter, University of Gent
R. Frye, Lucent Technologies
W. Menzel, Ulm University
R. Mittra, University of Illinois
O. Palusinski, University of Arizona
T. Sarkar, Syracuse University
J. C. Liao, Intel Corporation
R. Sturdivant, Hughes Corporation
R. Tummala, Georgia Institute of Technology

General Information

Registration

For Short Courses - Sunday, October 26, 1997

Registration will be held in the Foyer of the Catalina Ballroom of The
Wyndham Hotel, 1350 N. First Street, San Jose, CA 95112-4789 beginning
at
7:00 a.m. Registration fee for Short Courses 1 and 2 is $275.00 each
and
for Short Courses 3, 4, 5 is $375.00 each. Registration fee includes
course material and a refreshment break.

For The Meeting - October 27 - 29, 1997

Registration will be held in the Foyer of the Catalina Ballroom of The
Wyndham Hotel, 1350 N. First Street, San Jose, CA 95112-4789 on Sunday,
October 26, 1997 from 8:00 am to 5:00 p.m. and resumes on Monday,
October
27th at 7:00 a.m. The registration fee for IEEE members prior to
October
10th is $395.00 and after October 10th is $415.00; non-members prior to
October 10th is $500.00 and after October 10th is $550.00; 1 Day
registration is $250.00; Students and IEEE Life members is $200.00. The
fee includes the conference digest, refreshment breaks, luncheons, and a
Monday evening welcoming reception.

Walk-in registrations will be accepted only on a space-available basis.

TECH MUSEUM - Tuesday, October 28, 1997

The Tech Museum of Innovation provides a contemporary setting combined
with highly imaginative exhibits. Upon opening The Tech was named one
of
the top ten new attractions in the United States.

For guests who are curious about technology and science and hot it
affects
their lives, The Tech is a fantastic choice. Where else could you have
a
pleasant business discussion followed by a robot drawing your portrait,
a
simulated low-level flight over the surface of Mars or a chance to
design
your own bicycle at a CAD/CAM workstation?

Accommodations

A block of rooms has been reserved for participants at The Wyndham
Hotel,
1350 N. First Street, San Jose, CA 95112-4789, phone 408-453-6200. The
hotel is offering a special rate of $119.00 plus 10% tax for single or
double occupancy. Reservations must be made by September 26, 1997 to
receive these rates. After this time reservations will be accepted on a
space available basis only. Please be sure to mention you are attending
the EPEP '97 Conference.

Additional Hotels

The Airport Inn International, 1355 N. Fourth Street, San Jose, CA
95112,
phone 1-800-453-5340, fax 408-453-5208 is holding a block of rooms at
$89.00 plus tax, single or double occupancy. Room rate includes
complimentary airport shuttle service from the San Jose Airport and
complimentary continental breakfast. Reservations must be made by
September 26, 1997 to guarantee this rate. Be sure to mention you are
attending the EPEP '97 conference.

The following hotels are near the Wyndham Hotel. Call the hotels for
details.

Best Western San Jose Lodge, 1440 N. First Street, San Jose, CA 95112,
phone 408-453-7750.

Executive Inn-Airport, 1310 N. First Street, San Jose, CA 95112, phone
408-453-1100.

TRANSPORTATION

The Wyndham Hotel provides complimentary transportation between the
airport and the hotel.

Additional Information

Contact the conference co-chairs:

Vijai K. Tripathi - e-mail: vkt@ece.orst.edu
phone: 541-737-2988 FAX: 541-737-1300

A. Deutsch - e-mail:deutsch@watson.ibm.com
phone: 914-945-2858 FAX: 914-945-2141

or conference administrator:

P. Baltes - e-mail: epd@engr.arizona.edu
phone: 520-621-3054 FAX: 520-621-1443

Conference Web Page

Updated information on the conference can also be found on the
following web pages:

http://intermix.engr.arizona.edu/~epd/#EPEP
http://www.cpmt.org/epep/home.html
http://www.webcom.com/uw_web/alina.html

San Jose

San Jose is the capitol of the Silicon Valley, the mecca of the nation's
high technology industry. It is a dynamic city celebrating an extensive
downtown renaissance. Many original 19th century structures still stand.
Some 125 parks and gardens grace the city. One highly unusual
attraction
is the beautiful, bizarre Winchester Mystery House with its labyrinth of
160 rooms and mind-boggling architectural oddities.

Sunday, October 26, 1997

Foyer of California Ballroom

7:00 - 8:00 a.m. Registration for Short Courses 1, 2, 3

8:00 a.m. - 5:00 p.m. Registration for Short Courses 4, 5, and Meeting

Salon E

8:00 a.m. - 10:30 a.m. Short Course 1
Introduction To Electromagnetic Interference Design And Modeling,
John H. Magerlein and Albert E. Ruehli, IBM Corp.

10:45 a.m. - 12:45 p.m. Short Course 2
Transmission-Line Effects In On-Chip Interconnections,
Alina Deutsch, IBM Corp.

Salon M

8:00 a.m. - 12:00 noon Short Course 3
Electrical Design for Signal Integrity of Digital Systems,
Paul Franzon, North Carolina State University
Salon E

1:30 p.m. - 5:30 p.m. Short Course 4
High-Speed Interconnect and Package Modeling Using Finite-Difference
and Finite-Element Methods,
Andreas C. Cangellaris and Jiaming Jin,
University of Illinois at Urbana-Champaign

Salon M

1:30 p.m. - 5:30 p.m. Short Course 5
IC Package and PCB Interconnect Characterization and Modeling,
Edward Godshalk, Maxim Corp.
Dima Smolyansky, Cascade Microtech, Inc.

Monday, October 27, 1997

Foyer of the California Ballroom

7:00 - 8:30 a.m. Registration

Salon J-M

8:30 - 8:45 a.m. Introduction/Welcome

8:45 - 10:25 a.m. Session I - System Design Issues

Session Chair: Vijai Tripathi, Oregon State University

The Electrical Challenges of Packaging the IBM AS/400 - (Invited) -
Gerald
K. Bartley, Paul E. Dahlen, IBM Corp., USA

Design Methodology for Chip-on-Chip Applications, Yee L. Low, Robert
C. Frye and Kevin J. O'Connor, Lucent Technologies, USA

S/390 Cost Performance Considerations for Packaging Choices - (Invited)
-
George Katopis, Wiren D. Becker, IBM Corp., USA

Large-scale Optical Backboard Bus, Satoru Yamaguchi, Tsuyoshi
Hayashi, Yukiharu Ohno, and Tetsu Mikazuki, NTT Opto-electronics Labs,
Japan

Salon F

10:25 - 10:55 a.m. Break - Refreshments

Salon J-M

10:55 - 12:45 a.m. Session II - Power Distribution Design Issues

Session Chair: Ravi Kaw, Hewlett-Packard

Packaging and Power Distribution Design Considerations for a Sun
Microsystems Desktop Workstation - (Invited) - Larry D. Smith, Sun
Microsystems, USA

EMI and Power Delivery Design in PC Systems, Dennis Herrell,
Advanced Micro Devices, USA; Benjamin Beker, U of South Carolina, USA

Delta-I Noise Avoidance Methodology for High Performance Chip
Designs, Moises Cases, Bhupindra Singh, Howard Smith, IBM Corp., USA

Importance of Damping and Resonance in Thin-Film Integrated
Decoupling Capacitor Design, Jaya Bandyopadhyay, Premjeet Chahal
and Madhavan Swaminathan, Georgia Institute of Technology, USA

Low-Cost Technique for Reducing the Simultaneous Switching Noise in
Sub-board Packaging Configurations, Shinji Koike and Katsumi Kaizu, NTT
Network Service Systems, Labs., Japan

Salon A-E

12:45 - 2:20 p.m. Lunch (for Meeting attendees and guests with tickets)

Salon J-M

2:20 - 3:30 p.m. Session III - On-Chip Interconnect Parameter
Extraction

Session Chair - Paul Franzon, North Carolina State University

On-Chip Interconnect Modeling Technologies - (Invited) - E. Aykut Dengi,
Motorola, Inc., USA; Ronald A. Rohrer, Technology Modeling
Associates, USA

Improving the Accuracy of On-Chip Parasitic Extraction, Ching-Chao
Huang, Kyung Suk (Dan) Oh, Shun-Lien Wang, Sridhar Panchapakesan,
Technology Modeling Associates, Inc., USA

3D Global Interconnect Parameter Extractor for Full-Chip Global
Critical Path Analysis, S.Y.Oh, K. Okasaki, J. Moll, O.S.
Nakagawa, N. Chang, Hewlett Packard Labs, USA

Salon F

3:30 - 4:00 p.m. Break - Refreshments

Salon J-M

4:00 - 5:00 Session IV - On-Chip Noise Analysis

Session Chair - John Prince, University of Arizona

The Importance of Inductance and Inductive Coupling for On-Chip
Wiring, A. Deutsch, H. Smith, G.A. Katopis, W.D. Becker, P.W. Coteus,
C.W. Surovic, G.V. Kopcsay, B.J. Rubin, R.P. Dunne, T. Gallo, D.R.
Knebel, B.L. Krauter, L.M. Terman, G.A. Sai-Halasz, P.J. Restle,
IBM Corp., USA

Experimental Electrical Characterization of On-Chip Interconnects,
Barbibrata
Biswas, Alan Glasser, Steven Lipa, Michael Steer, Paul Franzon, Dieter
Griffis, Phillip Russell, North Carolina State U, USA

A Hierarchical Power Supply Distribution Model for Full-Chip Switching
Noise Analysis, Howard H. Chen, IBM Research Div., USA

Salon F

6:00 - 7:30 p.m. Session V - Open Forum (Posters)

Session Chair - Paul A. Baltes, University of Arizona

Reduction of High-Speed Signal Distortions in Double-Layered Dielectric
PCB Interconnects, T.R. Gazizov and N.A. Leontiev, Tomsk State U of
Control Systems & Radioelectronics, Russia

A New Technique for the Extraction of SPICE-type Equivalent Circuits
from Measured or Computed-S-parameters of Microstrip Components and
Discontinuities, Pingjuan L. Werner and Raj Mittra, Penn State U, USA

High Frequency Characterization of Interconnection on Glass Fiber
Inforced PCB (G30), A. Owzar, C. M. Weickhmann, Deutsche Telekom AG,
Germany; F. Fazelpour, Rockwell Semiconductor Industry, USA;
P. Windirsch, J. Reimers, Deutsch Telekom AG, Germany; H. Reichl,
Frauhofer-Institute for Reliability and Microintegration Berlin, Germany

The Enhancement of Static Simulator Package Characterization Through
Conductor Segmentation, Guy Klemens, Vladimir Aparin, Kevin Gard,
QUALCOMM, Inc., USA

Numerical Modeling of Inductance for a Distributed System, Roger
Gravrok,
Sequent Computer Systems, USA; Andrew Byers and Melinda Piket-May,
U of Colorado, Boulder, USA

Packaging and Interconnect Design and Analysis using FTDT, Melinda
Piket-May, U of Colorado, Boulder, USA; Kevin Thomas, Cray Research,
USA; Roger Gravrok, Sequent Computer Systems, USA

Wideband Crosstalk Analysis of Coupled Bondwires Buried in High-Speed
Plastic Packages, Sang-Ki Yun and Hai-Young Lee, Ajou U, Korea

A New Flip-Chip Mounting Technique for High Temperature Operations,
Ananjan Basu and Tatsuo Itoh, UCLA

Special Types of Coplanar Transmission Lines Suitable up to mm-Wave
Bands, Jiri Svacina, Institute of Radioelectronics, Czech Republic

Characterization, Modeling, and Optimization of High Power Module
Packaging, Malay Trivedi and Krishna Shenai, U of Illinois at
Chicago, USA

Tuesday, October 28, 1997

Salon J-M

8:00 - 9:20 a.m. Session VI - Simultaneous Switching Noise Modeling

Session Chair - George Katopis, IBM Corporation

A Simultaneous Switching Noise Analysis of a High Speed Memory Module
Including the Test Environments & System-level Models, Joon-Ho Choi,
Kyung-Hwa Kim, Jung-Bae Lee, Taek-Soo Kim, Jeong-Taek Kong and
Sang-Hoon Lee, Samsung Electronics Co., Ltd., Korea

Effects of Floating Conductive Plane on Effective Inductance, J. L.
Prince, U of Arizona, USA; Michael Lopez, Intel Corp., USA

Flip-Chip Redistribution Layer Electrical Characterization and
SSO Noise Simulation, Zhonghua Wu and Ascar Siguenza, LSI Logic Corp.,
USA

Characterization of Peripheral and Core SSOs in a Flip-Chip Package,
Ravindranath Kollipara, Lei Lin and Gary Oehrle, LSI Corp, USA

Salon F

9:20 - 9:40 Break - Refreshments

Salon J-M

9:40 - 11:00 a.m. Session VII - Crosstalk Simulation

Session Chair - Ken Lee, Hewlett-Packard

Validity Ranges of Crosstalk Models, Weimin Shi and Jiayuan Fang,
SUNY Binghamton, NY, USA

Simulation vs. Calculation of Crosstalk, Kenneth J. McClellan, Jr.,
Defense Special Weapons Agency, USA: Tom S. Wailes, Air Force
Institute of Technology, USA; Paul D. Franzon, North Carolina State U,
USA

Significance of Electromagnetic Coupling Through Vias in Electronics
Packaging, Jin Zhao and Jiayuan Fang, SUNY Binghamton, NY, USA

Adjacent Line Coupling for Long Off Chip Interconnects, Hubert Harrer,
Dierk Kaller and Erich Klink, IBM Deutschland Entwicklung GmbH, Germany

Salon F

11:00 - 11:20 a.m. Break

Salon J-M

11:2:0 a.m. - 12:40 p.m. Session VIII - Radiated Emissions & Coupling

Session Chair - Mahdavan Swaminathan, Georgia Institute of Technology

Modelling and Simulation of Electromagnetic Interference in Electronic
Circuits, Petra Nordholz, Hartmut Grabinski, U Hannover, Germany

The PSTD Algorithm: A Fast and Accurate Time-Domain Method for
Electronic Package Characterization, Q.H. Liu, New Mexico State U,
USA; Y.L. Li and J.C. Liao, Intel Corp., USA

Effects of Heat Spreader on Electrical Characteristics of Tape-BGA
Packages, Samil Hasan, Andreas Cangellaris, U of Arizona, USA;
Ravi Kaw, Hewlett Packard Co., USA; William Pinello, U of Arizona, USA

Study of Coupling Phenomena in Transmission Line Structures Covered
By Slotted Screens Using the Generalised Circuital Analysis, J.V.
Balbastre, M.Bort and L. Nuqo, U Politicnica de Valencia, Spain

Salon A-E

12:40 - 2:10 p.m. Lunch (for Meeting attendees and guests with tickets)

Salon J-M

2:10 - 3:10 p.m. Session IX - Characterization Techniques & Model
Verification I

Session Chair - Don DeGroot, National Institute of Technology

Characterizing N-port Packages and Interconnections with a 2-port
Network Analyzer, Stefaan Sercu and Luc Martens, U of Gent, Belgium

Characterization of Multiconductor Inhomogeneous Uniformly
Coupled Lines from TDR Data, Alok Tripathi and V.K. Tripathi,
Oregon State U, USA

Accurate Characterization of Board Level Interconnects for High
Performance Systems, R.D. Lutz, A. Tripathi, and V.K. Tripathi,
Oregon State U, USA; T. Arabi, Intel Corp., USA

Salon F

3:10 - 3:30 p.m. BREAK

Salon J - M

3:30 - 4:30 p.m. Session X - Characterization Techniques & Model
Verification II

Session Chair - Luc Martens, University of Gent

Accurate De-embedding of the Contribution of the Test Boards to the
High-Frequency Characteristics of Backplane Connectors, Stefaan Sercu
and Luc Martens, U of Gent, Belgium

Measurement and Field Simulation Based Characterization of Plastic IC
Packages, Ferenc Mernyei, Austria Mikro System International AG,
Hungary

Standardizable and Automated Procedures to Measure and Simulate Very
Complex 3D Packaging Parasitics with Highest Accuracy, Shown for a
TSOP50 as Example, E. Miersch, EFM Consulting, USA; S. Muff,
Siemens AG, Germany; M.G. Jin, Pacific Numerix Corp., USA

5:30 p.m. Buses leave for Tech Museum

Wednesday, October 29, 1997

Salon J-M

8:00 - 9:20 a.m. Session XI - Microwave Packaging I

Session Chair - Chong-Il Park, Kyocera America, Inc.

Simulation of Large Packaged Dense Microwave Circuits, Peter Petre,
George
Valley, Hughes Research Labs., Inc., USA; Robert T. Kihm, Hughes
Electronics Corp., USA: and Stephen D. Gedney, U of Kentucky., USA

Suppression of Leakage and Crosstalk in Typical Millimeter-Wave Flip-
Chip Packages, Gye-An Lee and Hai-Young Lee, Ajou U, Korea

A Novel Broadband Flip Chip Interconnection, Juno Kim, Dongsoo Koh,
and Tatsuo Itoh, UCLA, USA

Simulation and Performance of Passive Microwave and Millimeter Wave
Coplanar Waveguide Circuit Devices with Flip Chip Packaging, P. Petre,
M. Matloubian, Hughes Research Labs., Inc., USA; R.T. Kihm, Hughes
Aircraft Company, USA; and S. D. Gedney, Hughes Research Labs, Inc.,
USA

Salon F

9:20 - 9:40 a.m. Break -Refreshments

Salon J-M

9:40 - 11:20 a.m. Session XII - Microwave Packaging II

Session Chair - Tatsuo Itoh, University of California, Los Angeles

Buried Double Bondwires for Microwave Hermetic Packages, Sung-Jin
Kim and Hai-Young Lee, Ajou U, Korea

Ultra Low Loss Millimeter Wave MCM Interconnects, A. Pham, J. Laskar,
Georgia Institute of Technology, USA: V. Krishnamurthy, H.S. Cole and
T. Sitnik-Nieters, GE Corporate Research & Development Ctr., USA

Circuit Modeling of Isolation in Flip-Chip Microwave Integrated
Circuits,
Ryosuke Ito and Robert W. Jackson, U of Massachusetts, USA

A Method for Evaluating Effect of Package Resonances on Circuit
Performance, Haki Cebi, K.C. Gupta, U of Colorado, USA

Quasi-TEM Model for Coplanar Waveguide on Silicon, Dylan F. Williams
and Michael D. Janezic, NIST, USA; Andrew R.K. Ralston and R. Scott
List, Texas Instruments, Inc., USA

Salon A-E

11:20 a.m. - 1:00 p.m. Lunch (for Attendees and guests with tickets)

Salon J-M

1:00 - 2:50 p.m. Session XIII - Accelerated Modeling/Simulation I

Session Chair - Tawfik Arabi, Intel Corporation

An Introduction to the Fast-MoM `in Computational Electromagnetics -
(Tutorial ) - Ali R. Baghai-Wadji, Vienna U of Technology, Austria

Rapid Electromagnetic Analysis of Multilayer Interconnects, D.
Heckmann, S.L. Dvorak and A.C. Cangellaris, U of Arizona, USA

Improving the Efficiency of Multipole-Accelerated Method-of-Moments
Solvers Using Dual Grid Multipole Expansions, Jing-Rebecca Li and
Jacob White, M.I.T., USA

Utilization of Fast Algorithm to Analyze Embedded Passive Components
Using Commercial EM Solvers, Kwang Lim Choi and Madhavan
Swaminathan, Georgia Institute of Technology, USA

A Technique for Fast Calculations of Capacitance Matrices of
Interconnect
Structures, Vladimir Veremey and Raj Mittra, Penn State U, USA

Salon F

2:50 - 3:10 p.m. Break - Refreshments

Salon J-M

3:10 - 4:20 p.m. Session XIV - Accelerated Modeling/Simulation II

Session Chair - Alina Deutsch, IBM Corporation

Survey of Model Reduction Techniques for Analysis of Package and
Interconnect Models of High-Speed Designs - (Invited) - Eli Chiprout,
Tuyen Nguyen, IBM Austin Research Labs, USA

Time Domain Multiconductir transmission Line Analysis Using Effective
Internal Impedance, Sangwoo Kim and Dean P. Neikirk, U of Texas at
Austin, USA

Generating Reduced Order Models via PEEC for Capturing Skin and
Proximity Effects, Mattan Kamon, MIT, USA; Nuno Marques, L Miguel
Silvera, Instituto Superior Tecnico, Portugal; Jacob White, MIT, USA

Salon J-M
4:20 - 4:30 Closing Remarks
----------------------------------------------------------------------

Monday, October 27, 1997

8:30 - 8:45 a.m. Introduction/Welcome

8:45 - 10:25 a.m. System Design Issues

10:25 - 10:55 Break

10:55 - 12:45 a.m. Power Distribution Design Issues

12:45 a.m.- 2:20 p.m. Lunch

2:20 - 3:30 p.m. On-Chip Interconnect Parameter Extraction

3:30 - 4:00 p.m. Break

4:00 - 5:00 p.m. On-Chip Noise Analysis

6:00 - 7:30 p.m. Open Forum

Tuesday, October 28, 1997

8:00 - 9:20 a.m. Simultaneous Switching Noise Modeling

9:20 - 9:40 a.m. Break

9:40 - 11:00 a.m. Crosstalk Simulation

11:00 - 11:20 a.m. Break

11:20 - 12:40 p.m. Radiated Emissions & Coupling

12:40 - 2:10 p.m. Lunch

2:10 - 3:10 p.m. Characterization Techniques & Model Verification I

3:10 - 3:30 p.m. Break

3:30 - 4:30 p.m. Characterization Techniques & Model Verification
II

5:30 p.m. Buses Leave for the Tech Museum

Wednesday, October 29, 1997

8:00 - 9:20 a.m. Microwave Packaging I

9:20 - 9:40 a.m. Break

9:40 - 11:20 a.m. Microwave Packaging II

11:20 - 1:00 p.m. Lunch

1:00 - 2:50 p.m. Accelerated Modeling/Simulation I

2:50 - 3:10 p.m. Break
i
3:10 - 4:20 p.m. Accelerated Modeling/Simulation II

4:20 - 4:30 Closing remarks
----------------------------------------------------------------------

Short Course 1 - Sunday, October 26, 1997 from 8:00 a.m. - 10:30 a.m.

INTRODUCTION TO ELECTROMAGNETIC INTERFERENCE DESIGN AND MODELING

Lecturers

John H. Magerlein, Albert E. Ruehli
IBM Thomas J. Watson Research Center

OBJECTIVE

This short course will introduce the electronic package designer to the
fundamentals of radiated electromagnetic interference (EMI) and to
design and modeling techniques and tools which can minimize EMI. At
the conclusion of the course, the student should understand the
importance of package design decisions in reducing EMI and should be
familiar with the basic types of EMI design tools which are available.

CONTENT

The course will attempt to answer the following questions:

* What is electromagnetic interference, why is it important, and why
is it becoming a more difficult problem as clock frequencies increase?

* What are the factors in the design of an electronic package which
are likely to influence radiated EMI?

* What general types of design tools are available to the electronic
package
designer to help in making decisions regarding EMI? What are the
strengths and weaknesses of each type?

* What are the mathematical methods available for the rigorous
simulation
of EMI and what are the advantages and disadvantages of each?

* What is the best way to use rigorous simulation in EMI design? We
will
include examples of the successful use of simulation based on the
practical experience of the instructors.

The class will be run informally with time for questions from the
attendees.

INSTRUCTORS

JOHN H. MAGERLEIN is a Research Staff Member and
manager of the Electromagnetics and Thermal Analysis group at the IBM
Thomas J. Watson Research Center in Yorktown Heights, NY. He received
his MS and PhD degrees in physics from the University of Michigan and
worked for two years at Bell Laboratories before joining IBM. He
worked in materials and processing for experimental Josephson junction
circuits, GaAs MESFET processing and characterization, and the
characterization of advanced multi-chip modules prior to assuming his
present position in 1992. His present research interests include
development and application of advanced design tools for
electromagnetic interference (EMI) and electronic package analysis.
He has developed EMI design rules for IBM products, consulted on
electromagnetics issues, and instructed engineers from all parts of
IBM on the use of electromagnetics design tools. Dr. Magerlein is a
member of the American Physical Society and the IEEE.

ALBERT E. RUEHLI received the Ph.D. degree in electrical engineering
in 1972 from the University of Vermont, Burlington.

He has worked at IBM on many different projects which include
mathematical analysis, semiconductor circuits and devices, and manager
of a VLSI design and CAD group. Since 1972, he has been at the IBM
T.J. Watson Research Center, Yorktown Heights, NY, where he now is a
Research Staff Member in the electromagnetic analysis group.

He has served in numerous capacities for the IEEE. In 1984-1985 he
was Technical and General Chairman respectively of the ICCD
International Conference. He has been a member of the IEEE ADCOM for
the Circuit and System Society and an associate editor for the Trans.
on CAD. He has given numerous talks at conferences and universities
and has organized many sessions.

He is the editor of two books, Circuit Analysis, Simulation and
Design(New York, North Holland 1986,1987) and he is an author or
coauthor of over 100 technical papers.

Dr. Ruehli received IBM Outstanding Contribution Awards in 1975,1978
1982, and 1995, and he received the Guillemin-Cauer Prize Award the
IEEE Circuits and System Society for his work on waveform relaxation in
1982. He is a fellow of the IEEE and a member of SIAM.

Short Course 2 - Sunday, October 26, 1997 from 10:45 a.m. to 12:45 p.m.

TRANSMISSION-LINE EFFECTS IN ON-CHIP INTERCONNECTIONS

Lecturer

Alina Deutsch
IBM T. J. Watson Research Center

OBJECTIVE

The intent of this short tutorial presentation is to introduce
the attendees to the need for taking transmission line effects
into account accurate delay and crosstalk prediction on short, medium,
and long on-chip interconnections. At the conclusion of the lecture,
the participant should understand the benefits of optimized
wiring cross section, control of inductance and resistance of
ground return path, performance-driven routers and wiring rules with
multiple constraints, wiring rules, and frequency-dependent equivalent
circuit synthesis for coupled lines.
The presentation should be of interest to the circuit designers
working on high-performance microprocessor chips and to package
engineers who want to help the chip designers achieve clock
frequencies close to 1 GHz and beyond.

CONTENT

The lecture is based on extensive modeling, simulation, and
experimental characterization of representative five- and six-layer
on-chip interconnection structures. The following topics will be
covered:

* Review of high-performance digital interconnections

* Brief theoretical explanation of transmission-line properties

* Three-dimensional modeling examples for R(f)L(f)C matrix extraction

* Frequency-dependent coupled transmission-line model synthesis

* Comparison of measured and simulated waveforms for representative
long coupled-line structures
* Effect of capacitive coupling for short wiring

* Effect of inductive coupling for medium and long lines such as data
buses
* Effect of inductance and resistance of ground current return path
for
long lines such as for clock distribution
* Performance constraints for wiring rules and routers
* Design guidelines to reduce negative results of transmisison-line
effects
* Material, fabrication, design, modeling, and simulation tool
improvement requirements

LECTURER

ALINA DEUTSCH received her B. S. and M.S.
degrees in Electrical Engineering from Columbia University, NY, and
Syracuse University, Syracuse, in 1971 and 1976, respectively. She
has been at IBM Watson Research Center since 1971 and has worked
in a number of areas, including testing of semiconductor and
magnetic bubble memory devices, packaging design, and on-chip
interconnect design and analysis. She is a Senior Engineer currently
working on the design, analysis, and measurement of packaging and
VLSI chip interconnections for future digital processor and
communication applications. In the past four years she has been at the
forefront of developing the understanding of transmission-line effects
in on-chip interconnections. She has designed, modeled, and
characterized
unique on-chip interconnect test vehicles under an ARPA contract
that have been transferred to SEMATECH. In this period, Ms. Deutsch has
published ten papers and given numerous invited talks at workshops
and conferences organized by SEMATECH, SRC, the IEEE
Solid-State Circuits Society, and IMAPS on the analysis of on-chip
transmission lines. Her work involves three dimensional modelling,
signal integrity analysis, noise simulation, and testing.
She has designed unique lossy transmission line configurations,
developed
unique high-frequency high impedance coaxial probes, and invented
a novel short-pulse measurement technique for characterization of
resistive transmission lines. A. Deutsch has written numerous papers,
holds 8 patents, and has received Outstanding Technical Achievement,
Research Division, and S/390 Division Team awards from IBM in 1990,
1993, and 1996. She is co-chair for the third year of the IEEE Topical
Meeting on Electrical Performance of Electronic Packaging, served as
guest editor of the IEEE Transactions on Components, Packaging, and
Manufacturing Technology, Part-B in 1996 and 1997, and is an associate
editor of Part-A. She is a member of Tau Beta Pi and Etta Kappa Nu,
and a senior member of the IEEE.

Short Course 3 - Sunday, October 26, 1997 from 8:00 a.m. to 12:00 noon

ELECTRICAL DESIGN FOR SIGNAL INTEGRITY OF DIGITAL SYSTEMS

Instructor

Paul Franzon
North Carolina State University

OBJECTIVE

The intent of this short course is to introduce the attendees to design
issues and solutions for the design of packages, PCBs, MCMs and ICs for
high speed digital systems. At the conclusion of the course
the student will understand the important issues related to
understanding
Signal Integrity and to how they are solved in digital systems. The
course is designed for the engineer who is relatively new to this
area and needs to know more.

CONTENT

The following topics will be covered:

o Signal Integrity in Digital Systems
- Definitions
- Noise sources and budgeting

o Modeling and Understanding of PCB, Package, and IC Interconnect
- Transmission line `effects'
- Choosing the required model accuracy

o Noise sources and their control
- Reflection Noise
- Crosstalk Noise
- Simultaneous Switching Noise

INSTRUCTOR

Dr. Paul D. Franzon is currently an Associate Professor in the
Department
of Electrical and Computer Engineering at North Carolina State
University.
He has over ten years experience in electronic systems design and design
methodology research and development. During that time, in addition to
his
current position, he has worked at AT&T Bell Laboratories in
Holmdel, NJ, at the Australian Defense Science and
Technology Organization, as a founding member of a
successful Australian technology start up company, and as a
consultant to industry, including technical advisory board positions.
Dr. Franzon's current research interests
include design sciences/methodology for high speed packaging and
interconnect, for high speed and low power chip design and the
application
of Micro Electro Mechanical Machines to electronic systems.
In the past, he has worked on problems and projects in wafer-scale
integration, IC yield modeling, VLSI chip design
and communications systems design. He has published over 50 articles and
reports. He is also the co-editor and author on a book about multichip
module technologies. Dr. Franzon's teaching interests focuses on
microelectronic systems building including package and interconnect
design, circuit design, processor design and the gaining of hands-on
systems experience for students.
Dr. Franzon is a member of the IEEE, ACM, and IMAPS. He was general
chair of the 1997 IEEE MCM Conference. In 1993, he received an NSF Young
Investigator's Award. Dr. Franzon received a BS in Physics and
Mathematics, a BE with First Class Honors in Electrical Engineering,
and a PhD in Electrical Engineering all from the University of
Adelaide, Adelaide, Australia.

Short Course 4 - Sunday, October 26, 1997 from 1:30 p.m. to 5:30 p.m.

Lecturers

HIGH-SPEED INTERCONNECT AND PACKAGE MODELING
USING FINITE-DIFFERENCE AND FINITE-ELEMENT METHODS

Andreas C. Cangellaris, Jiaming Jin
Department of Electrical and Computer Engineering
University of Illinois at Urbana-Champaign

OBJECTIVE

The purpose of this short course is to present the fundamental
attributes of "finite methods" such as the method of finite elements
and the finite-difference method, and explain why these attributes
make these methods so suitable for the electromagnetic modeling of
package- and interconnect-induced noise in packaged high-speed
electronics. The presentation will include parasitic extraction and
package-induced noise, as well as results from on-going research on
these methods aimed at enhancing their modeling versatility and
computational efficiency.

CONTENT

* Introduction to Finite Methods

- Finite Difference vs. Finite Elements
- Frequency Domain vs. Time Domain Methods
- Static, Quasi-Static, and Dynamic Problems

* Frequency-Domain Finite Element Method (FEM)

- Fundamentals
- Numerical Grid Generation and Refinement
- Application to Package Parasitic Extraction
- Scattering-parameter Calculation for Package and Interconnect
Discontinuities
- Application to EMI/EMC Problems
- Fast-frequency sweep and Model-Order-Reduction using FEM Codes
- Capabilities of Commercially Available FEM Codes

* Finite-Difference Time-Domain Method (FDTD)

- Fundamentals
- Application to Interconnect Discontinuity and Package Modeling
- Application to EMI Analysis of Packaged Electronics
- Incorporation of Non-linear Drivers in FDTD
- Application to Simultaneous Switching Noise Analysis
- Application to Microwave Amplifier Design
- Capabilities of Commercially Available FDTD Codes
- FDTD vs. Finite Element and Finite Volume Time Domain Methods

Instructors

ANDREAS CANGELLARIS (M'86) received the Diploma in Electrical
Engineering
from the Aristotle University of Thessaloniki, Greece, in 1981, and the
M.S.
and Ph.D. degrees in Electrical Engineering from the University
of California, Berkeley, in 1983 and 1985, respectively. During the
period 1985-1987 he was with the Electronics Department of General
Motors Research Laboratories in Warren, Michigan. From 1987-1997 he
was with the Department of Electrical and Computer Engineering at the
University of Arizona, first as Assistant Professor (1987-1992) and then
as Associate Proffesor. In August 1997 he joined the University of
Illinois at Urbana-Champaign as Professor in the Department of
Electrical and Computer Engineering. Dr Cnagellaris' expertise and
research interests are in applied and computational electromagnetics,
high-speed electronic packaging, and microwave engineering. Over the
past ten years he has supervised the development of electromagnetic
software tools for the computer modeling of package parasitics and the
simulation of pulse propagation in complex interconnect media in
high-speed electronic packages. Dr. Cangellaris is author or co-author
of over 100 scientific journal and conference papers in the areas
of computational electromagnetics, microwave engineering, and modeling
and
simulation of high-speed interconnects. he is an active member of the
following IEEE socities: Antennas and Propagation; Microwave Theory and
and Techniques; and Components, Packaging and Manufacturing Technology.
He is co-founder of the IEEE Topical Meeting on Electrical Performance
of Electronic Packaging, which is sponsored jointly by the IEEE
Microwave Theory and Techniques Society and the IEEE Components,
Packaging and Manufacturing Technology Society.

JIAN-MING JIN received the B.S. and M.S. degrees in Applied Physics
from Nanjing University, China, in 1982 and 1984, respectively, and
the PhD. degree in Electrical Engineering from the University of
Michigan, Ann Arbor, in 1989. He joined the faculty of the Department
of Electrical and Computer Engineering at the University of Illinois at
Urbana-Champaign (UIUC) in 1993 after working as a Senior Scientist at
Otsuka Electronics (USA), Inc. Currently he is an Associate
Professor and Associate Director of the Center for Computational
Electromagnetics at UIUC. He has published over 50 articles in
refereed journals, authored the book, The Finite Element Method in
Electromagnetics, (Wiley, 1993), and co-authored another book,
Computation of Special Functions, (Wiley, 1996). His Current research
interest include computational electromagnetuics, scattering
and antenna analysis, electromagnetic compatibility, and magnetic
resonance
imaging.Dr. Jin is a senior member of IEEE and an associate editor
of the IEEE Transactions on Antennas and propagation. He is a recipient
of the 1994 National Science Foundation Young Investigator Award,
and the 1995 Office of Naval Research Young Investigator Award. He also
received a 1997 Xerox Research Award from UIUC College of Engineering.

Short Course 5 - Sunday, October 26, 1997 from 1:30 p.m. to 5:30 p.m.

IC PACKAGE AND PCB INTERCONNECT CHARACTERIZATION AND MODELING

Instructors

EDWARD GODSHALK, MAXIM CORP., DIMA SMOLYANSKY, CASCADE MICROTECH, INC.

OBJECTIVE

The intent of this short course is to address important issues of
measurements and equivalent circuit model extraction for the
interconnects in the IC packages and PCBs. Both time and frequency
domain measurements are discussed, and the model extraction and model
verification techniques based on these measurement are presented.
Probing and fixturing issues, that are critical to the measurement
accuracy, are addressed . The role of E&M and standard SPICE-type
simulators in the model verification is discussed.

The course is designed for engineers and researchers who work on
interconnect characterization and signal integrity design and who
are interested to understand how to perform accurate repeatable
measurements of interconnects, as well as learn the interconnect
modeling and model verification techniques.

CONTENT

This course is based on instructors' experiences in interconnect
characterization and modeling, as well as recent research in the area
of equivalent circuit model extraction from measurements.
The following topics will be covered:

* Role of interconnect measurements and modeling in the design
FLOW

* The physical nature of interconnects

* The approach to interconnect characterization

* Interconnect measurements

- Probing issues
- Time Domain Reflectometry fundamentals and true
impedance profile extraction
- Vector Network Analysis fundamentals

* Interconnect equivalent circuit model extraction from
measurements

- Lumped elements
- Distributed elements
- Coupled transmission lines
- Lossy transmission lines

* Equivalent circuit model validation

The information presented will require minimal knowledge of
transmission line theory and will be focused on practical aspects
of interconnect characterization and modeling. The techniques to be
presented are directly applicable to characterization and modeling
of any passive structures used in high speed/high frequency design,
such as package leads, board traces, connectors, cables and so on.

The class will be run informally and interaction with the attendees
is encouraged. Questions and discussions will be invited.

Instructors

ED GODSHALK is a Senior Characterization Engineer at Maxim Integrated
Products and is responsible for characterization and modeling of IC
packages. Prior experience include modeling and characterization of
high-speed MCMs at Tektronix and inventing both the Air Coplanar (ACP)
wafer probe and waveguide input wafer probe while working at Cascade
Microtech. He has published many technical articles on wafer probing,
MCM characterization, phase noise, oscillators and other high-frequency
devices

DIMA SMOLYANSKI is a Senior Applications Engineer for high-speed,
RF and microwave applications with Cascade Microtech in Beaverton, OR.
He has several years of experience in high-speed passive and active
device characterization and measurements, including characterization
of IC packages and PCBs. Mr. Smolyansky has published several papers
in the area of interconnect characterization and taught part of the
short course on package measurements at the EPEP'95. He is also one
of the developers of the Interconnect Parameter Analyzer at Tektronix,
a pioneering integrated solution for interconnect characterization and
modeling. He holds a MS degree from Oregon State University, Corvallis,
OR and Electronics Engineer Diploma Degree from Kiev Polytechnic
Institute, Kiev, Ukraine

Registration Form

Participants are urged to register and thereby help the organizers
with planning.

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Short Course Registration Fee (Per Person/Per Course)

(Must register for short courses no later than October 10, 1997)

Course Number 1 $275 $----------
Course Number 2 $275 $----------
Course Number 3 $375 $----------
Course Number 4 $375 $----------
Course Number 5 $375 $----------

Meeting Registration Fee (Per Person)
(Includes digest, refreshment breaks, lunches, and reception)

IEEE members (prior to October 10) $395 $----------
IEEE members (after October 10) $415 $----------
Non-members (prior to October 10) $500 $----------
Non-members (after October 10) $550 $----------
One-day registrtaion $250 $----------
Students and IEEE Life members $200 $----------

Extra Luncheon tickets per day number-- @$25 $----------
Extra Reception tickets number-- @$25 $----------
Extra Digest number-- @$30 $----------

The Tech Museum (MUST REGISTER BY OCTOBER 10)

Conference Attendees $28 $----------
Guests number-- @$40 $----------
Total Enclosed $----------

WALK IN REGISTRATIONS WILL BE ACCEPTED ON A SPACE AVAILABLE BASIS ONLY
Please make check payable to:
The University of Arizona Foundation

Note: registration fees are not a tax deductible contribution. However,
they may be deductible as a business expense. Check with your accountant
or tax advisor.

The University of Arizona accepts American Express, Visa or Mastercard:
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Persons with a disability may request reasonable accommodations, such
as sign language interpreter, by contacting Engineering Professioal
Department, 520-621-3054. Requests should be made as early as
possible to allow time to arrange the accommodation.
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Mail/FAX/Email this form to:
Engineering Professional Development
The University of Arizona
1224 N. Vine Avenue
Tucson, AZ 85719-4552
520-621-3054 FAX: 520-621-1443
email: epd @ engr.arizona.edu

Product Displays:
Parties interested in displaying products at this meeting should
contact the address above.