Re: Power/ground connections/bypassing on ICs

Larry Smith (ldsmith@lisboa)
Fri, 9 May 1997 13:14:44 -0700

Howard - I agree with most of what you are saying in your note to
the si-list. I thought I would write a personal note back to you
to discuss a few things, rather than get the whole si-list involved.

> First, consider the chip as a source of noise.
> The output impedance of the chip (the effective
> driving point impedance of the chip's Vcc and Gnd
> pins) is always GREATER
> than the Vcc/Gnd impedance of a properly designed
> board (if it's not, then you have a whopping
> huge amount of Vcc/Gnd noise). This ratio
> is what controls Vcc/Gnd noise.

I am pretty sure that the power supply as seen from the chip terminals
(pads, bumps or whatever) is higher than the chip power supply impedance
at some frequencies. There is always some inductance in the packaging
and some parasitic (and maybe intentionally designed) decoupling
capacitance on board the chip. This makes a fairly high Q resonant
circuit. After all, we have done our best to get any resistance out.

In my experience, the resonance of this circuit is between 50 and 100
MHz. The inductances keep going down and the capacitances keep going
up. The resonant frequency 1/(2pi*Sqrt(LC)) doesn't change too much
from generation to generation. If the chip tries to draw current from
the the power supply at the resonant frequency, bad things happen, like
lots of Vdd and ground noise. This can happen for example if a
processor does something for a few clock cycles, then stops doing it,
over and over. It is data and code dependent. The power supply, as
presented to the chip, has a high impedance at resonance.

> If you wish to prevent a noise chip from interfering
> with the reset of your system, here is a better approach:
> The Vcc plane (A) connects through inductor (B) to
> a bypass capacitor (C). Tbe bypass capacitor has a
> short-wide connection (aspect ratio 1:1 or less) to
> the VCC pin (D).
> The Gnd plane connects through a via directly
> to the bypass capacitor (E).
> The Gnd plane connects through a via directly
> to the chip GND pin (F).
> +----------+
> ###| |###
> | |
> ###| |###
> (A) (B) (C) | (D) |
> Vcc plane X==== L ====###=###| VCC |###
> | | | |
> Gnd plane X=### ###|=X GND |###
> (E) | (F) |
> ###| |###
> +----------+
> I.C.
> This arrangement reduces noise flow in both directions, from
> the system into the chip, and from the chip into the system.
> Ground bounce is conquered because I have provided a low
> impedance via from the GND pin (F) to the Ground plane.
> Vcc bounce is conquered because I have provided a low
> impedance path from the VCC pin (D), through the
> bypass capacitor, to its gound via (E).

We have used the above technique successfully to isolate a sensitive analog
circuit from a potentially noisy digital power plane. There is a danger
here because the inductance of the trace and package, and the capacitance
of the decap and chip parasitics form a L-C-L-C filter. Once again, resistance
is small so it is a fairly high Q circuit. There will be poles and zeros in
this 'power filter'. If the chip demands current at a 'high impedance'
frequency, we can have trouble. Also, transients will occur when we start
to draw current or stop drawing current.

With the power supply voltages coming down and the and the watts dissipated
going up, I believe that power distribution will be the next major challenge
in our business. I hope to publish more on this at a package design workshop
in Hilton Head this June and again at the EPEP next October. I thought I would
send these thoughts along to you to see if you had any comment.

best regards,
Larry Smith
Sun Microsystems