Re: [SI-LIST] : SSO in ASICs

nirmal@ansoft.com
Fri, 22 Aug 1997 12:54:34 -0400

Hi John,

John V Fitzpatrick wrote:
>
> Hello,
>
> Does anyone know of a paper or application note which gives
> design rules for the sizing of ASIC I/O strength and Vdd/Vss
> pin count, based on the notion of distributed, rather than lumped
> loads.

There is a very good reference on Simultaneous switching
Noise by Senthinathan and Prince. Here are the complete details:

Title: Simultaneous switching NOse of CMOS devices and Systems
By Ramesh Senthinathan and John Prince
ISBN 0-7923-9400-3

> When our ASIC designers estimate the number of Vdd/Vss pin pairs
> that are needed for a particular design, they apply the foundry's
> rules for SSO noise limitation.
>
> The founder's rules are very sensible: stronger buffers with fast
> edges mean more Vdd/Vss pairs. However, I'm not convinced by
> the relationship with load capacitance i.e. that the greater the
> capacitive load, the more Vdd/Vss pairs are needed, due to the
> fact that the capacitive load is distributed.
>
> Does a load at 20cm from the source really affect SSO noise?
> I don't think so. But at 10cm? 5cm?
>

In CMOS, if you look at the switching current thru the
Vss and Vdd, the maximum leading edge di/dt
would be "almost" the same for all these capacitive loads.
This is due to the fact that the through current when
both the P and N transistor are on momentarily, depends
on P and N transistor design (Channel L, W and
oxide thickness). However the trailing edge di/dt, which occurs
when this through current is turned-off and total switching
current is controlled now by the discharging current would
obviously depend on the load capacitor. Trailing edge di/dt
for larger load capacitances would be smaller than smaller
load capacitances. The resistance of the line length
would tend to reduce the switching noise.

regards

Nirmal

> I would be more at ease with a rule which took into account the
> impedance of the line being driven, rather than the total
> capacitance. I believe that such a rule would lead to a
> lower, and truer, estimation of the number of supply pins needed.
>
> Any opinions?
>
> Thanks in advance,
> John
>
> --
> John Fitzpatrick <John.Fitzpatrick@ln.cit.alcatel.fr>
> Alcatel Telecom, 4 rue de Broglie, 22304 Lannion, France
> Tel: +33(0)2.96.04.79.33 Fax: +33(0)2.96.04.85.09