[SI-LIST] : Non-ideal return current paths
Mon, 20 Jul 1998 09:44:22 -0700
I am working in a PC board environment with rise-times < 1ns. A number
of my signals have to switch between layers referenced to different
planes. This means a less-than-ideal ground return path exists for
I have added some decoupling between planes within an inch of the vias
where this occurs, but it was only a guess as to how much I needed.
Also, I suspect that if many such signals switch at once, their return
currents must all share the same few caps simultaneously, thereby
multiplying the voltage induced across the ESL of the caps.
I'm looking for advice on quantifying the effects of my non-ideal
return paths on the propagation delay and shape of high-speed signals.
Any good references?