RE: [SI-LIST] : IBIS Model Verification

Abe Riazi (ariazi@anigma.com)
Tue, 15 Sep 1998 22:22:43 -0700

Nik Bannov Wrote:

>>
>>Can't anybody explain me what is the use of
>>Vmeas, Cref, Rref, and Vref
>>parameters in IBIS. In other words, how simulator can/should use them.
>
> ---------------
> /
> /- V_meas
> /
>------
> ->| |<-
> delta_t
>
>>Does simulator need a parameter(s) to adjust so the user
>>can control delta_t = time from low to V_meas?
>>How about waveforms V(t) (and/or ramps), don't they
>>impose timing restrictions.
>
>>Thanks a lot for any clarification on this issue.
>
>>Nik Bannov
>
>nikolai@avanticorp.com
>
>
>
Hi Nik:

Vmeas, Cref, Rref, and Vref are parameters used by the IC manufacturers
when specifying
the propagation delay and/or output switching time of a device. More
specifically:

Vmeas= Reference voltage for timing measurements.
Cref= Test Load capacitance value for timing measurements ( Cref
connects between output of driver and GND)
Rref= Test Load resitance value for timing measurments (Rref
connects between output of driver and Vref)
Vref= Test load voltage for timing measurments.

A recent email by Weston Beal includes additional information regarding
these parameters.
You can also obtain more information related to Vmeas, Cref, Rref, and
Vref by referring to IBIS Specification documents available on the IBIS
web site:

http://www.eia.org/eig/ibis/ibis.htm

To my understanding, Vmeas, Cref, Rref, and Vref, are NOT used during
creation of an IBIS model to generate any of the waveforms (i.e. pullup,
pulldown, rising/falling, etc.) of the model (unlike, for example
V_fixture and R_fixture which are utilzed for generation of
Rising/falling
waveforms). The values of these parameters should be the same as those
given in the AC timing section of the device's data sheet.
If Vmeas, Cref, Rref and Vref are missing in the IBIS model or if their
values differ from those speicfied in the data sheet,
then the values given in the data sheet should be used towards generaion
of the topology and model files required for the calibration runs.
The following paragraph explains further why these parameters should be
taken into consideration during the course of a simulation:

In a simulaton, in order to obtain correct flight times it is essential
that the measurement be taken from the right point
every time. In QUAD this is referred to as Vm (manufacturers
measurement voltage) . As stated previously all timing measurements (for
example values given for Thold, Tsu, etc.) in an IC's data sheet are
taken at a certain voltage (Vm) using a given (test) load. As an
example, the output delay of an asic may be based on Vm=1.5 v into a
capacitive test load of 50pF. Flight times need to be measured in the
same fashion. The simulator, however, will measure the trace delay as
the time the driver (buffer) begins to drive until the time it reaches
the receiver at the upper or lower threshold voltage. The time required
by the signal to reach the Vm from when it started driving is called
"Time to Vm" or "rated load timing". To accomplish a match between the
Vm point of the flight time and the measurement point of Thold, Tco,
etc., the time to Vm must be subtracted from the trace delay times.
QUAD models, which are generated from IBIS models via IBIS2XTK program,
include values for Time to Vm; however, the values require verification.
Furthermore, for a digital pulse, the Vm correction is needed for both
Low to High and High to Low transitions of the signal.

I hope you find this information helpful.

Regards,

Abe Riazi
SI Engineer
Anigma, Inc.

email: ariazi@anigma.com

>

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