Re: [SI-LIST] : Decoupling Capacitors

Mark Randol (ryvw50@email.sps.mot.com)
Mon, 13 Apr 1998 09:27:02 -0700

Raman Muthukrishnan wrote:
> - Will there be a problem if the VCC and GROUND via from
> the power pins of a chip are shared with the corresponding
> vias of the decoupling capacitor placed close to those
> power pins ? The chip is on the top layer and the decap is
> on the bottom layer..

It would be alot better if you put the cap on the same side
as the part. The inductance will be lower that way. The
idea of a bypass cap is to create a low impedance source
at the bypass point. Putting the extra via inductance in
doesn't help that. Also, at higher frequencies if you don't
connect the cap before you make a connection to power and
return ("GND"), it's gonna get on 'em.

Depending on your frequencies, the currents involved, the
susceptability of other circuits, you might get away with it,
but it isn't optimum. Unless there is a compelling reason
not to, I'd put the cap on the same side as the part, as close
as you can get it.

The next question is, "How do you pick a decoupling cap?"

-- 
---------------------------------------------------------------
Mark Randol, RF Measurements Engineer   | Motorola SPS, Inc.
(602)413-8052 Voice                     | M/S EL379
(602)413-4150 FAX                       | 2100 E. Elliot Road
ryvw50@email.sps.mot.com                | Tempe, AZ 85284
---------------------------------------------------------------