Do you mean a daisy-chained differential clock net? I think that you
may not like what you see. First, you will be introducing skew to the
clock signals by virtue of each load being a different distance from the
driver. Second, each load will present a capacitive discontinuity to
the transmission line, creating a reflection. I would think that if
you're worried enough about common-mode noise to use differential
clocks, you will probably want to cluster as few loads as you can get
away with at the end of the net where parallel termination can help
suppress the reflection. A daisy chain topology will probably negate
the benefits of using a differential clock.
If you want to do some quick simulations to check out the differences in
net topologies, driver types, and terminations, check out Motorola's web
site. I believe you can get SPICE models of their ECL clock drivers.
Greg
----------
Greg Edlund , Principal Engineer
Alpha Server Signal Integrity
Digital Equipment Corp.
129 Parker St. PKO3-1/20C
Maynard, MA 01754
(508) 493-4157 voice
(508) 493-0941 FAX
[email protected]
>----------
>From: fabrizio
>zanella[SMTP:fabrizio=zanella%Eng%[email protected]]
>Sent: Wednesday, April 09, 1997 9:25 AM
>To: [email protected]
>Subject: Differential clock
>
>Hello SI engineers,
>I understand the benefits of using differential pairs for signals running
>at 100MHz and above. Can anyone speak about the impact of using
>differential clocks in a parallel bus, though? Do the differential clocks
>maintain the noise suppression characteristics when daisy chained in a
>multidrop environment?
>Has anyone tried this and had positive experiences vs. single ended
>multidrop clocks?
>
>Thanks in advance,
>
>Fabrizio Zanella
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