Thank you for all those who replied. Sorry I was too busy (and still is) =
on this problem I don't even have time to reply right away.
First off I would like to thank you for all the inputs and ruls of =
thumbs. They are mostly consistant and confirmed what I have learned =
before. Changing the thickness of different layers is also a good =
suggestion and I am current considering it.
My Problem (firstly reflections and secondly, ringings) has not been solv=
e yet and I still need suggestions from experts like yourselves. The =
following are some details of situation:
-->
I just start routing a PCB for a controller board. There are Intel-type =
uC and DSP's. The PCB is about 8" in length and due to space limitation, =
the DSP's are distributed on one end of the PCB and the uC is on another. =
Before I start routing, I manually routed two signals almost =
side-by-side so when I do signal integrity simulation I could compare =
them. The tracks are switched back and fro between the two routing =
layers to match a real life situation. These two signals are driven by a =
74AC245 xcvr (originated from the uC) and branched to all DSPs. The =
final track is about 10-15" long. This is a 6 layer board with only two =
internal routing layers in the middle. From one DSP to another it is =
about 2" or so. BTW, locations of the DSP and the uC cannot be =
alternated (mechanical constrain for heat sinking).
I ran the simulation (UNISOLVE) and compared the two signals at the =
source and the end of the daisy chain, with one terminated with 100 Ohm R =
and 100 pF Cap, and another is not terminated. As I indicated earlier, =
the terminated signal is not much cleaner but the amplitude is way low(RC =
too large). I also tried different RC values and there isn't much =
improvement. I could restore the amplitude with smaller RC but the =
double edges are still there. I also tried T versus Daisy Chain and also =
tried source series termination. The best I could achieve is when using =
a 10-15 Ohm series termination with Daisy Chain configuration. However, =
some pins still have a small notch at the edge (some are up to 1 ns in =
duration).
I was using 1.6 ns rise time and a 10 MHz clock rate for the simulation. =
With the 2 to 3 times prop delay to rise time rule this is definitely a =
transimission line. With a 1/10 rule on stubs, I think I could not use =
them to branched between the DSP either.
There are a lots more signals which are similar to these two signals. I =
am using these two as a benchmark.
-->
After using the textbook solution of Daisy Chain and termination, the =
signal is still having ringing and double-edges. I think it is related =
to the mismatch bewteen layers, the drive capability, and the change in =
Z0 when devices are attached along the chain. The solution to the first =
constrain, my guess, would be using impedence controlled PCB and/or =
change the thickness of each layer for a better match. I may not able to =
use impedence controlled PCB due to cost issue. With the initial Zo's =
number I have, I think the reflection is very small from layer to layer =
anyway. I can't do much for the second constrain (the driving =
capbaility) unless adding more drivers. The last one, in theory, should =
be fixed by simply changing the match resistor value to the new Zo'. =
However, I have no luck on that.
I almost exhaust all my avenues to fix this problem. I have already =
keep all the tracks short (however, still too long ), daisy chained the =
devices, and try terminating. I haven't tried diode clamping yet and I =
will. Nevertheless, I would like to avoid them as they are physically =
bigger than a 0805 or 0603 chip. It also mostly for ringing, not for =
reflection.
I would like some more ideas or suggestions.
Thank you in advance for you help.
Regards,
Norman Wong
Hardware Design Engineer
Wireless Development Center, Nortel
email: [email protected]
--------------------------------------
Date: 4/22/96 9:45 PM
To: Norman Wong
From: [email protected]
----- E X T E R N A L L Y O R I G I N A T E D M E S S A G E -----
Normal,
I agree with all that Arpad said... Yes the bread and butter of SI. :-) =
You
really need a board level simulator to find the best solution. There are =
a lot
of variables. How many do you control? Somethings that were not =
mentioned are
drive strength and strategicly placed series terminators (R or L). Also =
you
need to know how forgiving you receivers are. Then once you think you =
have
a solution, margin it all with voltage, temperature, silicon, and PWB =
material
variations. Yup, looks like a full time job to me.
On Apr 22, 4:28pm, Arpad Muranyi wrote:
> Subject: Re: SI- Termination Comments Wa
>
> Text item:
>
> Norman,
>
> Your questions are addressing issues that is the bread and butter of =
every
> signal integrity engineer. There are lot of books out there which =
address these
> issues, including my good old favorite, the Motorola ECL Design =
Handbook.
>
> Everything you say in your EMAIL makes sense.
>
> The impedance will vary with distance to GND plane, but ~50~75 Ohms are =
in the
> range of numbers I have seen.
>
> If possible avoid changing layers.
>
> Chain topology is better than having stubs.
>
> Parallel terminations do draw DC current which normal buffers are not =
designed
> to do, so your Vol and Voh might be "loaded" depending on which supply =
you are
> using for your termination.
>
> 5 ns rise/fall times are more forgiving than 1 ns, but to decide what =
you can do
> you need to know the length of the trace also. This goes for the =
length of the
> stubs as well. With slower rise/fall times you can generally have =
longer stubs.
> The best, however, is not having stubs at all...
>
> There are no short, clear answers to these questions. Most often you =
need to
> run a lot of simulations and learn from the simulation results... Most =
of the
> questions you are asking can be answered by parameterized Monte Carlo =
type
> simulations and plotting the results in a statistical manner. This is =
how most
> of us figure out the best solutions and the design space for a given =
design,
> topology, loading condition, etc...
>
> Good luck,
>
> Arpad Muranyi
> Intel Corporation
> =
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D
> Subject: Time:3:44 =
=3D
> PM
> OFFICE MEMO SI- Termination Comments Wanted =3D
> Date:4/19/96
>
> I am currently working on a mid-speed (<50MHz) digital circuit pack and =
=3D
> would like to proper terminate some long lines(up to 15 inches). It =3D
> consists of CPU, DSP, SRAM, Flash etc. I am approaching the problem by =
=3D
> using Daisy-Chained tracks and AC terminations. There are some =
findings =3D
> that I would like your comments:
>
> 1. When using uncontrolled-impedance FR4 PCB, based on my calculation =
on =3D
> a 6 layer board, the micro-strip (8 mil) Z0 is about 75 Ohm and the =3D
> STRIPLINE Z0 is about 45 Ohm. That means a mismatch every time I =3D
> switch layers. Does anyone has experience on this? Does it matter for =
5 =3D
> ns rise time? How about 1ns rise time?
>
> 2. My EDA simulation package showed that after termination, my signals =
=3D
> do not look much cleaner. In fact, it look worse and seems to be =
loaded =3D
> down (Vpeak is about 3.5-4V instead of 5V). Does this make sense?
>
> 3. At want point could I use T instead of Daisy-Chain so that the stub =
=3D
> look like capacitance, no transmission lines? A lot of time daisy =
chain =3D
> line is longer than a treed line.
>
> All comments on this matter are welcome.
>
> Thank you.
>
> Norman Wong
> Hardware Design Engineer
> Nortel, Wireless Development Center, Calgary
>