RE: [SI-LIST] : 3.3V Design

Andrew Ingraham (Andrew.Ingraham@digital.com)
Fri, 14 Aug 1998 15:44:54 -0400

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>What about 1.8V / 2.5V devices ? Is special layout needed? What about
>connectivity between other devices on the system?

We have been biting the bullet with mixed supply designs for some
years now. It's not surprising to find ourselves now with perhaps
four logic supply voltages on one board. It can get messy, just
keeping it all straight.

The big problem is with the interfaces between different voltage
domains. Some lower-voltage ICs are tolerant of inputs that go
over their supplies; others are not, and some of those will clamp
above their supply voltage. Pay close attention to the data sheets.
A 3.3V IC with a max Vin spec of 5.5V doesn't necessarily make it
tolerant of 5V inputs; overshoot can far exceed 5.5V, especially
since such a part has no input overshoot clamp diode.

Bus-hold inputs at the voltage-domain interface might cause
interesting problems. A bus-hold input is a weak output and
could back-drive a tri-stated low-voltage output pin above its
max Vout spec (but maybe not enough to damage it).

Also watch for lower-voltage ICs with true CMOS switching levels
as opposed to LVTTL levels. The latter are much more common with
3.3V supply ICs, but not universal.

The faster switching speeds of some of the newer ICs is indeed
cause for a lot of concern. Reduced noise margins just make
your job more interesting.

Some of the EIA's JEDEC documents at http://www.jedec.org may
be worth a look.

Regards,
Andy Ingraham

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