Re: [SI-LIST] : Non-ideal return current paths

Vigliarolo Roberto (Vigliarolo@asamrt.interbusiness.it)
Thu, 6 Aug 1998 18:32:04 +0200

Hi, Peter
I'm very sorry for the delay but I've been in holiday and so I'm just
reding your question.
I think it can be useful to you reading
Bypass Capacitors, an Interview With Todd Hubing=20
that you can find at:

http://www.ultracad.com/articles.htm

> ----------
> Da:
> =
PETER_ARNOLD@hp-santaclara-om3.om.hp.com[SMTP:PETER_ARNOLD@hp-santacla
> ra-om3.om.hp.com]
> Inviato: luned=EC 20 luglio 1998 18.44
> A: si-list@silab.Eng.Sun.COM
> Cc: ARNOLD_PETER/hp-santaclara_om3@boi118.boi.hp.com
> Oggetto: [SI-LIST] : Non-ideal return current paths
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> Dear SI-List,
> =20
> I am working in a PC board environment with rise-times < 1ns. A
> number=20
> of my signals have to switch between layers referenced to
> different=20
> planes. This means a less-than-ideal ground return path exists
> for=20
> these signals.=20
> =20
> I have added some decoupling between planes within an inch of =
the
> vias=20
> where this occurs, but it was only a guess as to how much I
> needed.=20
> Also, I suspect that if many such signals switch at once, their
> return=20
> currents must all share the same few caps simultaneously, =
thereby
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> multiplying the voltage induced across the ESL of the caps.
> =20
> I'm looking for advice on quantifying the effects of my =
non-ideal
>=20
> return paths on the propagation delay and shape of high-speed
> signals.
> =20
> Any good references?
> =20
> peter arnold.
> =20
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