Based on the number of responses from members of the list that could not
read the Word file that was attached to the last message, I am copying the
full text below. My apologies to those that now have to throw it away for
the second time.
To the participants of the Signal Integrity reflector:
This is a solicitation/invitation to participate in a new standards effort.
Frustration in the gathering of data for use in simulation and validation of
designs has led directly to this effort. Other member s of our corner of
the engineering community have encouraged it, so here we go.
Distribution of information about the electronic devices has moved forward
to the point where much/most of the COMPONENT DATA SHEETS are delivered via
the web or CD's or other electronic means. This change is driven by the cost
of publishing a data book and the cost of distribution of printed material
and will accelerate in the future with the decreased life cycle of the
components. This is the opportunity to remove translation errors and
actively request the information needed to support the CAD, CAM, and CAE
efforts. This data sheet standard would augment the normal paper/PDF data
sheet with information that can be parsed to meet the needs of CAE.
Initial concept is that this will be a VHDL like structure, to prevent
stepping on proprietary interests, and still be subject to exact extraction
of the required information by simple scripts for conversion to:
1. Schematic Captures programs - Concept, Orcad, Mentor, Viewlogic, Protel
and the like.
2. PCB Layout tools - Mentor, Allegro, Orcad, PADs, etc.
3. Simulation Tools - Spice, Quad, SpectraQuest, etc
4. Timing Verification Tools - Motive, Timing Designer etc.
5. Thermal Modeling tools -
6. Physical Design and Modeling tools - ME10, Solid Modeler, AutoCad, etc.
7. Other tools that you can think of, that I have missed.
Validation of the information distributed in this manner will be required
and an electronic signature will be included. Some companies will want to
change the data to meet their own internal design rules and can resign the
document with the company signature to validate the changes to those to whom
that may be distributed. This will, at least, allow verification of the
source of the information.
This project would lead to an IEEE STANDARD ELECTRONIC COMPONENT DATA
SHEET. The sponsor will be the Microprocessor Standards Committee.
PURPOSE
To create a international standard for Electronic Component DATA SHEETS
ranging in complexity from a "LED" to a "MERCED", that presents the device
information to the design engineer, and component engineer, in a structure
that easily converted into required data for electronic design and
simulation tools.
SCOPE
The information content would be the mechanical, electrical, timing,
topological, architectural and programmatical interface of the product being
described. Current standards, and proposed standards, will be used whenever
possible.
GOALS
Data is Certifiable from vendor - signed with encrypted signature
Modifiable by user to meet local needs - signed by user for local usage
Structured for interpretation by design tools - common source for all tools.
Formal but flexible format
Easily human readable - more ADA than C - VHDL proposed as basis.
Long Comments can be included - May include PDF pictures and diagrams like
current data sheets
Support individual devices - resistors to integrated circuits - LED's
Support assemblies - DIMM's, Processor Boards, Modules - Merceds
DATA REQUIREMENTS
MECHANICAL
Size of package(s)
Footprint(s)
Clearance Requirements
Bonding requirements
Soldering requirements
Mechanical specifications
weight, max acceleration
THERMAL
Heat distribution - thermal stress
Power usage as a function of usage
Thermal model for heat transfer
leads - Conduction
heatsink requirement
Heat flow Theta JA Theta JC
Maximum and Mimimum die(s) Temperature
ELECTRICAL
Pin Definitions and Pin Names - Possible standard symbol for schematics
VHDL ENTITY equivalent
Pin DC and AC specifications (IBIS) and Spice models
Power Consumption, Static and Dynamic
Pin parasitic topological specification
RLC and / or Transmission Line format
Emissions and Susceptibility
TIMING
Timing model for design verification
Delays
Setup and Holds
Clock to out
Single cycle timing
Multi-cycle timing
Asynchronous and Synchronous timing
"MOTIVE" like description
TOPOLOGICAL
Subcircuit Topology
DIMM boards
Processor Modules
TAB specifications
Hybrid Specifications
Similar to Quad Topology file
Cross Talk Characteristics
Magnetic and/or Capacitive coupling
ARCHITECTURE
What the part does
VHDL Architecture descriptor
What Model parameters are useful for simulation?
What else is needed for extended modeling?
PROGRAMING INTERFACE and MODELS
Addressing the inside parts
Register specification
C-style " header file" information
CONTRIBUTORS to Effort
Design Tool firms
Assembly houses
Chip Suppliers
Simulation Software vendors
USERS
A formal format will be needed for the above information, proposals and
contributions are solicited. The above list will be modified and
supplemented by the working group.
As much of the committee work as possible will be handled via a email
reflector. Some meetings will be required. All IEEE standards working
committee requirements will be followed.
If you are interested in WORKING on this effort please respond by email to:
Bob Davis
Summit Computer Systems, Inc
408-353-2706
[email protected]
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