These are some really good questions. Providing a set of pin usage
rules for an ASIC is a tough job. In my experience, SSO noise is very
dependent on the load -- certainly for the turn-on transient. You'll
want to know exactly what your ASIC vendor's assumptions were in writing
the rules and then determine if they are applicable to the net
topologies you have in mind. It may be the vendor is trying to give you
some guidelines to "keep you out of trouble." Pursuing the question
further than that may get into deeper waters. For example, how
sensitive are you to SSO-induced delay modulation? Does the vendor have
a spec for this? How about other noise contributors? If the vendor's
SSO rules push you to the limits of the receiver's noise margins, is
there room for PCB crosstalk? Connector crosstalk? Package crosstalk?
What exactly were the criteria for determining acceptable SSO noise?
Depending on how far you're pushing your technologies, you may want to
get a fully-coupled package model and SPICE subcircuits of the drivers.
Then you can simulate the real system loading and how SSO noise
interacts with your net topologies. Then there's the whole question of
model validation, which is no picnic. How well do you trust your ASIC
vendor's silicon and package modeling capabilities?
I don't mean to seem overly pessimistic. It may be that you don't need
to go to all this trouble. But it certainly pays to look into the SSO
rules and whether they are relevant to your application, as you've
already begun to do. As one of my co-workers used to say, "If it were
easy, they'd get monkeys to do it!"
Greg Edlund , Principal Engineer
Alpha Server Signal Integrity
Digital Equipment Corp.
129 Parker St. PKO3-1/20C
Maynard, MA 01754
(508) 493-4157 voice
(508) 493-0941 FAX
>From: John V Fitzpatrick[SMTP:John.Fitzpatrick@ln.cit.alcatel.fr]
>Sent: Wednesday, August 20, 1997 10:58 AM
>To: Signal Integrity Mailing List
>Subject: [SI-LIST] : SSO in ASICs
>Does anyone know of a paper or application note which gives
>design rules for the sizing of ASIC I/O strength and Vdd/Vss
>pin count, based on the notion of distributed, rather than lumped
>When our ASIC designers estimate the number of Vdd/Vss pin pairs
>that are needed for a particular design, they apply the foundry's
>rules for SSO noise limitation.
>The founder's rules are very sensible: stronger buffers with fast
>edges mean more Vdd/Vss pairs. However, I'm not convinced by
>the relationship with load capacitance i.e. that the greater the
>capacitive load, the more Vdd/Vss pairs are needed, due to the
>fact that the capacitive load is distributed.
>Does a load at 20cm from the source really affect SSO noise?
>I don't think so. But at 10cm? 5cm?
>I would be more at ease with a rule which took into account the
>impedance of the line being driven, rather than the total
>capacitance. I believe that such a rule would lead to a
>lower, and truer, estimation of the number of supply pins needed.
>Thanks in advance,
>John Fitzpatrick <John.Fitzpatrick@ln.cit.alcatel.fr>
>Alcatel Telecom, 4 rue de Broglie, 22304 Lannion, France
>Tel: +33(0)2.96.04.79.33 Fax: +33(0)2.96.04.85.09