Re: [SI-LIST] : bypass cap question (long, simple)

Philip Gantt ([email protected])
Mon, 02 Feb 1998 14:27:48 -0800

I think that you are correct when signals change layers so that the
image current must switch from one reference plane to the other, then a
path must be provided for the image current to flow. In your 4 layer
case, a capacitor is the only way to achieve this. However, in a
multilayer board where the two signal layers are sandwiched between
ground planes, a simple via would suffice.

In addition, I agree with Vinu's idea of using a single split power
plane for both 3.3 V and 5 V. I would however, add capacitors between
the voltages on this split plane to provide a path for the image
currents resulting from signal traces that cross the split in this power
plane. You could also reduce the end cost of the board by reducing the
number of layers to 7 instead of 8 by using a split power plane. Thus
your stackup could look like this:

1 Horizontal
2 V33 Plane/V5 Plane
3 GND Plane
4 Vertical
5 Horizontal
6 GND Plane
7 Vertical

Thus, signals switching between layers 4 and 5 would not need a
capacitor to provide a path for the image current, instead a via between
the ground planes would suffice, providing it is in close proximity to
the signal via.

Lawrence Butcher wrote:
> Imagine that I build a 4 layer board. Imagine that there were two chips on
> it, labeled U1 and U2. Imagine that I route the board strictly manhatten
> style. All horizontal wires are on top above the ground plane, and all
> vertical wires are on the bottom below the power plane.
> _______________
> | |
> | U1 ------* |
> | | |
> | | |
> | | |
> | U2 |
> |_______________|
> Normally, I would put bypass caps under U1 and bypass caps under U2.
> I would cosy them up so that there was minimum distance between the
> caps and the power supply pins on the chip.
> Consider the image currents running on the power and ground planes.
> An image current will sit directly under each wire. But that current
> will have a hard time following the wire through the via, because it
> would have to hop from the ground plane to the power plane.
> It seems clear that a capacitor might be needed at that via site to
> give the current in one plane a chance to hop to the other. Even
> though there are no components nearby.
> Intuition rarely substitutes for calculation. Question: Is this true?
> How much capacitance? How does that vary if there are 40 wires instead
> of 1? How does the number change with frequency?
> The above illustrates a real problem. I am building an 8-layer board,
> with a tentative stackup of:
> 1 Horizontal
> 2 GND Plane
> 3 V33 Plane
> 4 Vertical
> 5 Horizontal
> 6 V5 Plane
> 7 GND Plane
> 8 Vertical
> My component placement places all of the 3 volt components above the
> midline of the board, and all of the 5 volt components below the midline.
> Therefore, there are NO bypass caps from the 5V plane to ground in the
> top half of the board, and NO bypass caps from the 3.3V plane to ground
> in the bottom half of the board.
> A trace running horizontally on layer 5 in the top half of the board
> will have an image current running on the V5 plane, and that current
> has no way to get to the ground plane at a via site. Same for traces
> running on layer 4 in the botton half of the board.
> I want to add about 1 cap per square inch (about 50 more bypass caps).
> Half will be between V5 and ground in the top half of the board, and half
> will between V33 and ground in the bottom half of the board.
> These components are there only to deal with my paranoia about image
> currents. They would be placed even though there are already tons of
> bypass caps in the same area, but exclusively to only one power plane.
> My coworkers have doubts. They especially don't like 50 more caps when
> there are no nearby chips connected to the power planes I am concerned with.
> Most of my signals are changing at 100 MHz, but there is a bunch of 33 MHz
> activity running around. (Fast, for me).
> Is this a non-existent problem, or a real one? Comments?
> Lawrence

Philip R. Gantt   [email protected]                .           .       
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