Re: [SI-LIST] : Excessive clock overshoot

fabrizio zanella (
Thu, 14 May 98 8:24:13 -0400

I apologize for not giving enough information on yesterday's email about
the FCT clock overshoot. The termination at each end of the bus for these
clock lines is thevenin 100-5V/220-gnd. The loaded round trip delay is
about 4.4ns, so 2.2ns one way.
Hope this helps, thank you very much for the comments thus far.
The comment from Andy Ingraham about the FCT clock resonating at 45MHz does
make sense because on a receiver card at the clock input we see
oscillations/non-monotonic signals.
Would the resonance be caused by the internal clock circuitry or the load
it's driving?

Regards, Fabrizio Zanella.
EMC Corporation
Original Text
From: "D. C. Sessions" <>, on 5/13/98 5:23 PM:
To: smtp@Eng@EMCHOP1["SI-List" <si-list@silab.Eng.Sun.COM>]
Cc: smtp@Eng@EMCHOP1["SI-List" <si-list@silab.Eng.Sun.COM>]

fabrizio zanella wrote:
> I have a question regarding an FCT clock (TTL levels) driving a heavily
> loaded backplane. On the driver pin we see excessive overshoot on the
> transition which increases as we increase the clock frequency. This
> overshoot goes from 5V at 33MHz to 6.5-7.0V at 45MHz. The stub impedance
> is 75 ohms, backplane impedance 25 ohms loaded. There is a clamping
> on the H-L side but not on the L-H. The H-L side does not have any
> undershoot.
> I have asked the manufacturer and they have never seen this phenomena,
> do they have an explanation for it.
> Any ideas on what could be causing this?

1) Is the line unterminated?
2) Is the loaded one-way delay anything near 2.7ns?

D. C. Sessions