Computer simulation is rapidly becoming an essential phase of modern
high speed digital design.
IBIS (I/O Buffer Information Specification) models are well suited for
use in conjunction with several powerful
simulation programs including XTK from Quad Design/Viewlogic. IBIS
models are of behavioral type (Unlike
SPICE which are silicon models), and can potentially provide accuracy
comparable to SPICE at substantially
higher simulation speeds. These models are also popular with IC
vendors, because they do not disclose
information regarding internal circuiry, and vendors usually furnish the
IBIS models to simulation engineers.
Naturally the quality and accuracy of IBIS models can be critical to
the integrity of simulation results.
Before using an IBIS model in a simulation, first I check the model for
possible syntax /format errors using
the ibis_chk program, followed by an examination of the I-V data and
rise/fall times for monotonic behavior (with
the aid of the Visual IBIS Editor software). However, this level of
evaluation can prove insufficient in some cases.
Therefore, I am interested to learn about procedures and tools which
allow a comprehensive verification of an
IBIS model, thereby minimizing the possibility of unreliable simulation
Thank you in advance for your response.
**** To unsubscribe from si-list: send e-mail to email@example.com. In the BODY of message put: UNSUBSCRIBE si-list, for more help, put HELP. si-list archives are accessible at http://www.qsl.net/wb6tpu/si-list ****