What about the ESR of a chip's parasitic input capacitance? We had
a big discussion about that in the gigabit ethernet group about
a year ago, and nobody really ever came up with a
satisfactory answer. Is it .1, 1, 10, or 100 ohms?
At 04:13 PM 2/16/98 -0700, you wrote:
>Mark Nass wrote:
>> Does anybody have an accurate way of modeling package parasitics,
>> in particular in a QUAD simulation environment. I have been using
>> a lumped inductance for a BGA & SQFP package but find this to be very
>> inaccurate with fast edge rates and small voltage level swings. The ringing
>> from the inductor causes the signal to cross switching thresholds in the
>> simulation environment, but this ringing is not seen on the lab bench.
>> My feeling is that a specified ZO, TPD & and Length should be used
>> for the bonding wire, trace on the BGA package and the pin.
>> Does anybody have any thoughts on what values I could use for
>> the bonding wire?
>Bondwires are actually very good inductors. The package itself
>may be a PWB in implementation (consider BGAs). A good figure
>for bondwire inductance is 40uH/in.
>One of the reasons that many simulations show excessive ringing
>on ICs is that the capacitors are too high-Q. Most semiconductor
>capacitances (such as the ESD structures on I/O circuits) have
>quite large ESRs. Your best bet would be to correlate the ESR
>to the lab data.
>D. C. Sessions
Dr. Howard Johnson, Signal Consulting, Inc.
tel 425.556.0800 // fax 425.881.6149 // email firstname.lastname@example.org
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