Re: [SI-LIST] : Decoupling capacitor selection & placement

Michael Nagel (mina@force.de)
Wed, 29 Oct 1997 09:38:16 +0100

Just a comment on your use of multiple capacitors. It is not so simple to
use multiple capacitors for decoupling. You create resonances with the parasitics
of the capacitor plus the pcb traces and the parasitics of the component you
intend to decouple. At higher frequencies where the highest value capacitor
starts behaving as an inductuance you have a parallel resonance. This case is to
avoid dimensioning and choosing your decoupling capacitors. The layout is also
very important in this case. In a bad case you end up having resonant peaks of
impedance in your decoupling path. A simulation of the intended layout is necessary
to avoid this. I don't know to what frequency you intend to go, but with a proper
dimensioned decoupling using three capacitors you can go well beyond 300MHz while
the impedance stays below 1.5 ohms. No objections in general against this method,
but I think here we leave the area where rules-of-thumb are valid.

Regards
Michael

> From fred@luxtron.com Wed Oct 29 08:57:12 1997
> Date: Tue, 28 Oct 1997 23:26:30 -0800
> From: Fred Townsend <fred@luxtron.com>
> MIME-Version: 1.0
> To: Andrew Phillips <andrew@atri.curtin.edu.au>
> CC: SI-LIST <si-list@silab.Eng.Sun.COM>
> Subject: Re: [SI-LIST] : Decoupling capacitor selection & placement
> Content-Transfer-Encoding: 7bit
>
> You have hit upon one of my favorite interview questions. I rarely get
> the correct answer from recent grads because our schools don't teach
> this important subject. Bypass capacitors are necessary because of
> trace and lead inductance and di/dt, the changing current in the
> circuit.
>
> Bypasses are usually applied on a prophylactic basis without regard for
> their proper functioning. Therefore the application is almost always
> wrong, but not so wrong that anyone would notice. In part because there
> is no such thing as too many bypass capacitors.
>
> 0.1 uf caps typically have a self resonate frequency, the frequency
> where a capacitor stops being a capacitor and becomes an inductor, of
> somewhere between 10 and 50 MHz depending upon lead length. Ground
> inductance usually reduces the effectiveness far below 10 MHz.
>
> Simply, a bypass must be large enough to supply the instantaneous di/dt
> and small enough to be below the self resonate frequency. The higher
> the current, the larger the bypass capacitor. The higher the di/dt
> (frequency) the smaller the capacitor. This frequently results in
> impossible locus of values.
>
> The answer is to use multiple capacitors at different sizes. For
> instance, the close in (to the circuit) value might be somewhere between
> 1000pf and 10 nf, followed by a 0.1uf ceramic and finally a 22uf
> tantalum at the power entry point for the circuit.
>
>
>
> Andrew Phillips wrote:
> >
> > Hello,
> >
> > Please forgive me if my questions have been asked a million times before
> > ...
> >
> > When using decoupling capacitors to provide a low-impedance path between
> > power and ground it appears to be well-established that we must do the
> > following:
> >
> > - from device Vcc pin we drop a via to Vcc plane with as short a
> > connection as possible (to minimize lead inductance). Same for device
> > Gnd pin.
> > - from capacitor pads we also drop vias to Vcc and Gnd planes with very
> > short connections.
> >
> > What is the ruling for how close the capacitor needs to be to the device
> > Vcc and Gnd pins?
> >
> > For a device such as a microprocessor with multiple Vcc and Gnd pins,
> > how do we determine how many capacitors will be required?
> >
> > Many references suggest that using 1 x 0.1 uF cap per Vcc-Gnd pair is a
> > good rule-of-thumb - how is this value determined, and are there
> > situations when it is invalid?
> >
> > Thanks for any help,
> >
> > Andrew Phillips
> > Cooperative Research Centre for Broadband Telecommunications &
> > Networking
> > Perth, Western Australia
> >
> > p.s. anyone interested in the Texas Instruments TMS320C6x DSP, please
> > check out my info site:
> >
> > http://www.atri.curtin.edu.au/~andrew/DSP_Design/tms320c6x.html
> >
> > ------------------------------------------------------------------------
> >
> > Andrew Phillips <andrew@atri.curtin.edu.au>
> > Design Engineer
> > Cooperative Research Centre for Broadband Telecommunications & Networking
> >
> > Andrew Phillips
> > Design Engineer <andrew@atri.curtin.edu.au>
> > Cooperative Research Centre for Broadband Telecommunications & Networking HTML Mail
> > GPO Box U1987 Work: (618) 9266 3273
> > Perth Fax: (618) 9266 3244
> > Western Australia Netscape Conference Address
> > 6001 Netscape Conference DLS Server
> > Australia
> > Additional Information:
> > Last Name Phillips
> > First Name Andrew
>