I have some questions and maybe some among you can share your
experience with me if you'd like.
Our product is PC chipset, so we need to make demo boards to show to
our customers, however, due to the area on the PCB is now getting
smaller, so for some of the DRAM clk nets, we sometimes need to route
some clk nets on the internal layer(we are using 4 layer structure,
s-p-g-s), and the system seem to fine with this, however, some customers
asked that what is the impact on EMI with such trace layout structure. I
haven't done any experiment or comparison on this regard, so I can't
answer it, though I have learned from some seminar that putting clk net
into internal layer will help the EMI, however, will there be
degradations if there are a bunch of data or address signals on the
outer layer that are in perpendicular to the clk trace on the internal
layer, that means the return path is ruined because the trace on
internal layer will cut and split the power plane.
Any input will be highly appreciated, thanks!
Weber Chuang(ChingFu Chuang)
SI Engineer, System Team.
VIA Technologies. Taiwan, ROC.