Re: [SI-LIST] : Signal Integrity of 500 MHz on PCB

Katja Zuleeg (zk3317@nbgm.siemens.de)
Mon, 10 Nov 1997 11:21:53 +0100

Richard,

I read that You use the LineSim by Hyperlynx. Do you know for how long
it is possible to take a look at the program? I'm asking this because
I'm trying for about 3 months now to get a look and they told me (in
germany) that it's not available yet.

Thanks, Katja

RICHARD_BRUSH@hp-santaclara-om3.om.hp.com wrote:
>
> Yes, I have designed boards with ECLinPS logic at 500 MHz clock rates.
> I used a transmission line simulator (LineSim by Hyperlynx) to
> optimize the clock tree, PCB stackup, routing and terminations.
> Measured waveforms and signal delays were virtually identical to
> simulated values. I offer the following suggestions: