Re: [SI-LIST] : Decoupling capacitor selection & placement

D. C. Sessions ([email protected])
Fri, 31 Oct 1997 17:00:18 -0700

Michael Nagel wrote:

> Just a comment on your use of multiple capacitors. It is not so simple to
> use multiple capacitors for decoupling. You create resonances with the parasitics
> of the capacitor plus the pcb traces and the parasitics of the component you
> intend to decouple. At higher frequencies where the highest value capacitor
> starts behaving as an inductuance you have a parallel resonance. This case is to
> avoid dimensioning and choosing your decoupling capacitors. The layout is also
> very important in this case. In a bad case you end up having resonant peaks of
> impedance in your decoupling path. A simulation of the intended layout is necessary
> to avoid this. I don't know to what frequency you intend to go, but with a proper
> dimensioned decoupling using three capacitors you can go well beyond 300MHz while
> the impedance stays below 1.5 ohms. No objections in general against this method,
> but I think here we leave the area where rules-of-thumb are valid.

Snub. Losses are good. Add a mix of devices with high ESR (preferably
to the plane impedance) and good frequency response. The reason that
current designs don't ring like a bell is that the bypass devices are
actually quite lossy thanks to ionic dielectrics and thin conductors,
with the fact that the active devices (ICs) have quite a bit of
(N-well to substrate) and high-resistivity conductors (lightly doped

The net effect is of a distributed RC network, which will quench
a wide range of frequencies.

As an interesting experiment, try measuring the VDD-VSS capacitance
of a complex IC across frequency. It's voltage-dependent thanks to
the depletion-region geometries of N-/P- junctions, but at nominal
supply (3.3v) it's pretty impressive. It also has a nontrivial
ESR which, thanks to distribution geometries, can't be modelled

D. C. Sessions
[email protected]