[SI-LIST] : Future bus backplane

Garry Allen (garrya@abc.gov.au)
Fri, 05 Dec 1997 21:17:44 +1100

We are designing a system which is derived from futurebus using the 2mm amp
connectors. It is a synchronous time slice bus running at 12.5MHz. We are
planning to distribute the clock from the centre of the backplane with each
board having its own clock. Signal pins are alternated with ground pins
across the connector. We are also using Futurebus transceivers for the
address and data because of the control they provide.

We are now considering how the backplane is to be laid out. One question is
layer stackup. We need at least 6 layers. At a first pass we are
considering either

1.
Signal
Ground
Signal
very thick core
signal
Power
signal

or

2.
ground plane
signal
3V plane
signal
thick core
signal
5V plane
signal
ground plane

Would you care to comment on these please given that we also need to have
fairly uniform trace impedances

I do not want alternating signal/plane layers as we will have some
difficulties getting the backplanes manufactured.
Garry Allen
Australian Broadcasting Corporation
Ultimo
<garrya@abc.gov.au>