concerning the accurate modeling of vias it seems to me that
so called full wave electromagnetic field simulators will be
the only solution in the end.
Currently there are more or less two numerical methods available
for this purpose: the finite element method (FEM)
and the finite difference time domain method (FDTD). Whereas
FEM is well known for many years, FDTD is just beginning to
become a serious competitor. At our institute we are developing
and using such a FDTD code for packaging and interconnect
modeling. Typical results of FDTD simulations are time domain
curves of voltages or currents as they are recorded when a
pulsed signal is passing a via, bonding wire etc.. These curves
can be Fourier transformed to give S-,Z- or Y-parameters in the
frequency domain over the whole bandwidth of the signal.
Fitting these parameters to an equivalent circuit delivers you
all parasitics you suppose to be there.
Regards,
Ch. Schuster
-------------------------------------------------------------------
Christian Schuster, Dipl.-Phys. IIS, ETH Zurich
Integrated Systems Laboratory
Swiss Federal School of Technology Fax: +41 1 63 21194
Gloriastrasse 35 Phone: +41 1 63 27595
CH-8092 Zurich E-Mail: [email protected]
Switzerland WWW: http://www.iis.ee.ethz.ch/~schuster/
-------------------------------------------------------------------
> Andy,
>
> Thanks for your reply.
>
> At the present time, there exists a noteworthy problem, in simulation
> field, associated with accurate modeling of vias.
>
> In my opinion, there is a real need for simulation programs to possess
> the capabiltiy to model both the via capacitance and inductance. For
> example, I was recently involved in a high frequency (400 MHz)
> simulation task of tight time margin (sub 100 ps). Practically, every
> picosecond was precious and had to be accounted for. There was a
> concern for simulation accuracy because the program we use (QUAD)
> ignores the parasitic via inductance.
>
> It seems to me that a PCB database plus other files (such as Global
> Control File), which are utilized by a simulation program, contain
> sufficient information to allow for modeling of via inductance.
> Included in these files are information related to substrate dielectric
> constant and thickness, number and types of layers (i.e. board stackup),
> trace geometries, topology of the nets, and via dimensions.
>
> Therefore, it is surprising (and undesirable) that simulation
> algorithms omit via inducatnce and model a via as a purely capacitive
> entity.
>
> Regards,
>
> Abe Riazi,
> email: [email protected]
> >----------
> >From: Andrew Ingraham[SMTP:[email protected]]
> >Sent: Sunday, November 29, 1998 8:26 PM
> >To: Abe Riazi
> >Cc: '[email protected]'
> >Subject: RE: [SI-LIST] : Focusing on Parasitic Parameters
> >
> >> ... Perhaps one conclusion implied by your
> >>email is following:
> >>
> >> It is simpler to quantify parasitic via capacitance than via
> >>inductance.
> >
> >This is certainly true. It is easy to determine capacitance as a static
> >problem and typically it doesn't change much from its value at 0Hz.
> >
> >Determining inductance, on the other hand, requires you to define a
> >closed loop. You will get different answers depending on how you choose
> >the loop that includes your via. The inductive effect of the via may be
> >imagined as being partly in series with the signal trace, partly in
> >series with its return path, since the return current may need to spread
> >out when reaching the via, to find enough capacitance to flow from one
> >plane to another. It's an interesting 3D problem that doesn't easily
> >shoe-horn into a simple 1D solution.
> >
> >Regards,
> >Andy
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