Re: [SI-LIST] : Backplane Analysis / GTL Technology

Karthik Ethirajan (KarthikE@calmicro.com)
Wed, 23 Jul 1997 11:46:36 -0700

Intel GTL+ requirements (not much different from GTL):

0. Intel's pentium pro motherboard uses GTL+ - a controlled impedance
environment that supports high speed data transfers. In short, it is a
open-drain driver with pull-up/termination resistors to supply voltage

1. Intel uses controlled edge rate (~1nS)

2. Usually 5% tolerance pull-up termination in medium performance system; 1%
tolerance pull-up termination in high performance system

3. Voltage Specifications for GTL:
Vtt (supply) = 1.2V
Vol(max) = 0.4V
Vref = 0.8V
Vil(max) = Vref+50mV
Vih(min) = Vref-50mV
Vedge(min) = 0.3V/nS for GTL+
Vedge(max) = 0.8V/nS for GTL+

Some other references are ....

On GTL -----> www.asicasic.com/app_notes/GTL

On GTL+ -----> GTL+ app note, CMD Aug. 1996 Data Book

-Karthik
CMD

---------------------------------------------------------------------------------------------------
Karthikeyan Ethirajan
Applications Engineer (408) 934-3181

California Micro Devices 215 Topaz Street
karthike@calmicro.com Milpitas, CA 95035
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>>> Jim McNamara <jjm@dma.isg.mot.com> 07/23 10:43 AM >>>

Hi,

Has anyone done any backplane analyses using GTL technology?
I'm looking for any information, white papers, app notes, etc. addressing
multidrop backplanes using GTL bidirectional drivers & receivers. Any
information regarding the following would be greatly appreciated:

- attainable backplane speed vs. loading (# of slots)
- GTL problems / anomalies
- signal integrity / noise susceptibility
- ASIC vendors with GTL I/O (support for live insertion would be nice)
- preferred design parameters
- etc.

Thanks in advance,
Jim Mc

_______________________________________________________
Jim McNamara Phone: (508) 261-5025
Motorola ISG Fax : (508) 337-7173
20 Cabot Blvd. M4-10 Email: jjm@dma.isg.mot.com
Mansfield, MA 02048