[SI-LIST] : Synchronous SRAM Application

Jim McNamara (jjm@dma.isg.mot.com)
Wed, 15 Apr 1998 13:05:01 -0400

Does anyone have any experience with pipelined Synchronous SRAMs in ASIC
applications? I'm looking to clock the SSRAMs at 80 MHz. Two questions:

1. Should I focus on controlling (slowing down) the edge rates on address,
data, and control buses? Terminations everywhere seem too abundant. Or
should I just figure reflections into my flight time calculations? What
about EMI? I assume I will be terminating the clock. There is no physical
board layout or ASIC pinout yet.

2. What about multiple devices on the same bus? Assume 2 devices on the same
bus. A requirement is to perform back-to-back read cycles to different
devices. My concern is bus contention between devices. Given voltage and
temperature to be equal for both devices, the possibility of minimal bus
contention still exists; especially when clock skew, flight time, etc. is
figured into the equation. I was hoping to just tie the OEs low and use
the synchronous timing relative to the clock. But herein lies the problem.

I have no control over the clock-to-HiZ and clock-to-LoZ timing. Would it
be more prudent to drive separate OEs (asynchronous control) to each
In which case I could delay the turn-on times of the individual OEs. It
seems that this would work but it adds more pins to the ASIC which I'm not
sure I can afford. Any ideas? I plan on using the dual cycle deselect
(DCD) type devices (ref.Micron C5 device types). All memory accesses are
ADSC type accesses.

Wish List
What's the possibility I could push this to 4 devices on the same bus at
80 MHz? With the devices characterized at 30pf, I do assume some timing
degradation. But what am I missing? Where am I going to get burned if I
believe the timing works out? Am I totally off my rocker thinking about 4
devices on the same bus at 80 MHz? Candid opinions accepted. Are there
success stories? or failures?

Thank you,
Jim McNamara

Phone: (508) 261-5025
Email: jjm@dma.isg.mot.com