Please send your letter of inquiry and/or resume to:
Walt Arps
IBM
3605 Hwy 52 N
Rochester MN 55901
507.253.3963 voice
507.253.4966 fax
[email protected]
We are seeking candidates with all levels of skill and
experience, from
BSEE to experienced.
We currently have one position to fill in our group. We will
match your
experience, skills and interests with the tasks in our group. Your
responsibilities will be a time-varying mix of the tasks our group
performs. Currently, the major tasks in our group are:
A bus owner task. Bus owners are responsible for the
electrical design
and implementation of their system signals. The bus owner
selects the
vlsi drivers and receivers, determines the wiring topologies and
lengths necessary to meet the system performance goals. They
work with
the chip and package designers to insure that the implemented
signals
perform as they expect. The bus owner verifies their
expectations with
the system hardware during the hardware checkout, and the owner is
expected to investigate, debug and solve any problems in their
signals
in the hardware throughout the life of the product.
A chip-to-chip timing task. Chip-to-chip timers are responsible for
providing information to the chip designers about the delays
in all of
the signals between the chips in the system. This involves
participating in the evaluation, selection, implementation and
execution of delay calculation methodologies and tools. Timers are
responsible for creating and maintaining a common set of
modeling and
timing assumptions in support of the bus owners and their own delay
calculation activities. This also involves creating and maintaining
simulator models for the vlsi components and package
components in the
system being designed. Timers participate in the cycle time
estimation,
the noise estimation and budgeting for the system.
An I/O circuit design task. Designers are responsible for the
design,
layout and specification files to the chip design automation
system of
vlsi driver and receiver circuits in support of the system
performance
requirements. Designers also participate in the selection of
chip-to-chip interfacing and packaging strategies for future
systems.
We expect that you will have at least a BSEE with a solid
understanding
of the usual undergraduate course work in the time-domain
behavior of
transmission lines, the switching behavior of FET's, standard CMOS
digital interface circuit designs, and a working knowledge of
a circuit
simulator, such as spice. Of course, experience or advanced
coursework
you have with the tasks we need to accomplish is very helpful.
We also
expect that you can function well as part of a group of people
working
together for a common goal.
Our team is flexible with our work responsibilities, we help
each other
out, we work together without any hidden agendas or territory
disputes.
We are a results oriented group, and we continually evaluate
ourselves
searching for ways to improve our operation. We are successful,
influential and respected by our peers outside of our team. We have
designed, implemented and are shipping low-cost systems,
cost-performance systems, and very high performance systems - on
schedule with no hardware defects.
The AS/400, our product, is the most popular business computer
in the
world, with a large base of loyal customers, many partners who add
market value to our product and healthy margins for our business. We
have aggressive growth plans for our product with the investments in
resources to implement those plans.
Rochester is an affordable, comfortable mid-sized city in the upper
Midwest. Our economy has been growing steadily for at least the last
decade, driven by the strong regional, national and international
business of the Mayo Clinic and the consistent success of the AS/400
Division of IBM. Money magazine has consistently rated
Rochester as a
very livable city. We have good schools, and a community that
invests
in itself. We have abundant opportunities for outdoor and indoor
recreation and leisure time activities, both here in town, in the
surrounding area and in the nearby Twin Cities of Minneapolis and St
Paul.
Come join us.
Joe Cahill - VLSI Development