One way to derive a model for the delay lines is to use an 2.5D
full-wave Electromagnetic solvers. Commercial available tools
include Sonnet from Sonnet Software, MOMENTUM from HP-EEsof,
Strata from Ansoft, and IE3D from Zeland.
These tools solve full-wave electromagnetic fields in stratified
media and extract scattering parameters in frequency domain.
They all include the skin effect by using so called impedance
boundary conditions. By examine the phase of the transmission
coefficient (S12), one can obtain the dispersion characteristics of
the line. To use the model in time domain simulations, one needs
to figure out a way to convert to the s-parameters to an
equivalent circuit. I believe HP-EEsof provides such an utility though
it may require some tweaking.
Because those tools are specialized for stratified media, they are
very fast in general. For a typical delay line, it may only require
a couple of minutes per frequency on a SUN Sparc workstation.
-Xingchao Yuan, Ph.D.
Cadence Design Systems, Inc.
> From [email protected] Wed Sep 24 23:37 EDT 1997
> Date: Wed, 24 Sep 1997 17:49:21 -0700
> From: Michael Chin <[email protected]>
> To: [email protected]
> Subject: [SI-LIST] : Re: delay lines with PCB traces
> Cc: [email protected]
> Sender: [email protected]
> Content-Type: text
> Content-Length: 2232
>
> Brett,
>
> > From [email protected] Wed Sep 24 17:01:57 1997
> >
> > One suggestion in Howard Johnsons 'Black Magic Handbook': there is a
> > suggestion to implement delay lines with a chamfered corner or a rounded
> > corner. The argument is based on increased capacitance on a right-angle
> > due to the change in effective trace width. I am sure the praises have
> > been sung enough for this book, but I make sure all my designers get it.
> > A very good working understanding without wallowing in the e-mag world.
>
> Thanks for the reference to Howard's book. This was exactly
> what I did. In fact, by going to a wider gap, the rounded radius
> become more smoother. I followed this rule for all PCB trace corners,
> although a lot of my colleagues did not think that these would make
> a big difference.
>
> > Some additional questions:
> >
> > 1. Does anyone on the LIST have PCB design rules for this geometry
> > (serpentine) that they have validated on the bench? (e.g. not just a
> > rule of thumb)
>
> Well, I valididated on the bench the two delay line routings.
> The first case was a 4 mil trace with 6 mil gap in the serpentine,
> and about 10% decrease in the expected trace delay was measured.
>
> When the gap was increased to 24 mil in the serpentine, the trace
> delay was in line with our expectation.
>
> We did not have time to develop a PCB design rules but a rule of
> thumb I used is that as the trace gap is at least 3x the trace
> width, the coupling between two adjacent tracks dimenished to
> some insignificant level.
>
> > 2. Or, have a decent model to comprehend the effects of this geometry
> > (cross-coupling due to parallelism, any additional degradation of rising
> > edge, etc?)
>
> We once had suspected a coupling problem between two traces in
> a similar situation. And, we started to work on a model to
> simulation this behavior. But, after the trace gap was widen
> to 3x the width and the design worked, our energy was diverted
> to other areas. Thus, we never completed the modelling effort.
>
> What we learned was that this kind of coupling does occur even on
> slow signal (50Mhz range) if the edge rate was fast enough and
> the trace separation was not at least 3x the width.
>
> Michael Chin
> Cisco Systems, Inc
>