=09Please do not make spoil the sanctity
=09of a group to which people sign on for=20
=09information and knowledge exchange.=20
=09Not for receiving, as you very mildly put it,=20
=09"junk mail".
=09Its people like you who give the web a bad name.
=09I hope you desist from such activities in the future
=09and start using ethical means of finding people
=09to work in your organization.
=09
On Thu, 12 Feb 1998 [email protected] wrote:
-->
-->Sorry for the "junk" mail... but if any of you signal fidelity engineers
-->are available... please read on:
-->
-->=3D=3D=3D=3D
-->
-->My name is Steve Mango and I am the hiring manager of the Analog and
-->Signal Fidelity Group at Stratus (a fault tolerant computer design
-->company) in Marlboro, Ma. I have openings for signal fidelity engineers
-->to join my fast-growing team. I would prefer full time permanent
-->engineers, but I am willing to consider contractors.
-->
-->My group must solve many high-speed technical challenges as we push
-->clock and bus speeds >100MHz. I am looking for experienced signal
-->fidelity engineers to broaden my group. [Note: These positions are for
-->USERS of signal fidelity tools to solve complex problems, rather than
-->for software developers of new software analysis tools.]
-->
-->* Help define/diagnose/solve complex signal fidelity problems (clock
-->generation/distribution, interconnect design, timing, termination,
-->decoupling, power/ground distribution, package/connector selection,
-->etc.). =20
-->
-->* You should have at least 3-5 years experience in the signal fidelity
-->and high speed digital design field.
-->
-->* You should have hands-on experience with modeling and simulating with
-->Quad Design tools (MOTIVE, XTK, TLC), SPICE (PSPICE and HSPICE),
-->electromagnetic field solvers (e.g., Greenfield, Pacific Numerix,
-->Maxwell 3D, etc). Candidate should be familiar with high speed board
-->interconnect routers (Allegro and CCT router preferred). Experience with
-->IBIS modeling and Interconnectix software is a major plus. Candidate
-->should also be familiar with high speed test plan development, test
-->measurements techniques and lab equipment (HP and Tektronix). Experience
-->with current high speed processors and multiple logic families is
-->desirable. Other pluses are experience with custom ASIC cell design,
-->phase lock loops, hot plug, FET switches, PCI Bus, SCSI bus, and
-->web-based documentation.
-->
-->=B7 Education: BS degree minimum.
-->
-->It=92s an exciting time here at Stratus =20
-->
-->Come Join our team. =20
-->
-->Please call me at (508) 490-6231
-->Or email me at: [email protected]
-->
-->