Re: decoupling/ bypass capacitors at connectors
Dr. Edward P. Sayre (email@example.com)
Tue, 4 Mar 1997 21:31:32 -0500
The question of physical decoupling near connectors is a very interesting
subject and the comments made regarding capacitor rules of thumb are good.
However, a much more difficult problem awaits us all. The effect of
perforations in the ground and power planes due to fine pitch thru pin
connectors, and to some degree surface mount parts (QFP'sand some BGA's)
with their attendent vias. The loss of the web in the plane between the
"anti-pads" shows up as an increase in resistance as well as inductance. If
the web is perforated or becomes << pin spacing, the current will flow
around the perforated area which now appears as a slot. Any transmission
line currents that share the common path will couple through the inductance
and the result will be strong common mode coupling. Unless one knows that
this can happen, this noise destroys noise marging, affects timing by
changing the propagation delay and threshold crossing and will radiate if
there is sufficient energy present where the slot is a half wavelength.
I have personally seen the serious effects of perforated webs on a fast edge
TAXI chip that completly interrupted the I/O operation of a complete board.
The problem is just as bad for fine pitch surface mount devices and
connectors. Consider daughter cards mounted in surface mount 50 mil
connectors. If you line up the vias in a row because "neatness counts" the
effect will be to bisect the board. If the effect shows up at EMI test
time, very significant engineering re-design and material loss will be
suffered with the slip in schedule. This is the best reason for experience
in Signal Integrity and EMI to be in the same head.
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