si-list.mail by date
Starting: Wed 06 Dec 1995 - 11:37:40 PST
Ending: Sun 20 Jun 1999 - 03:56:60 PST
Messages: 2087
- New shareware Visual IBIS development tool for Windows Kellee Crisafulli
- Signal Integrity Position Open at Sun Microsystems Ray Anderson
- I/O Model opening at Intel Stephen Peters
- New version of Visual IBIS Editor V0.96 Kellee Crisafulli
- JOB POSTING Tomm V Aldridge
- source for IEEE and JEDEC docs Greg Edlund
- shield layer connection Joachim Mueller
- Re: shield layer connection Don Abernathey
- Re: shield layer connection [email protected]
- Re: shield layer connection Dr. Edward P. Sayre
- need some info..... Manjunath Shamanna
- Re: need some info..... Nirmal Jain
- Re: need some info..... Nirmal Jain
- Re: shield layer connection Dr. Edward P. Sayre
- Need free 2D mesh Generation Software Yun Li
- hiring Yun Li
- MCMC '96 Advance Program [email protected]
- Hello! Favorite pubs? Gary
- What a disappointment... patrick conway
- whadya know... Greg Edlund
- whadya know... Orlando Hernandez
- Eye Patterns F.Hart
- Re: Eye Patterns Greg Edlund
- Re: Eye Patterns Ray Anderson
- Re: Eye Patterns Tim Postel
- Re: Short Course: High Speed VLSI Interconnecti Don Abernathey
- Re: Short Course: High Speed VLSI Interconnecti Nirmal Jain
- More on Eye Patterns Ray Anderson
- More on Eye Patterns F.Hart
- eye pattern reading Greg Edlund
- Re: subscribe to si-list George Stevens/UB Networks
- Call for Papers ( EM Simuation Tools ) Walid Chamma
- Position Available Terry Morris
- impedance across ground plane Gary Peterson
- Re: impedance across ground plane Nirmal Jain
- Signal Integrity Position Open at Sun Microsystems Ray Anderson
- HFSS/Eminence User Group/Mail List Info Ray Anderson
- Happy Engineers Week!! F.Hart
- TX-Austin-Hardware Design Engineer Valerie Allen
- Signal Integrity Job:Austin,Texas-Hardware Design Valerie Allen
- Re[2]: impedance across ground plane Barry Ma
- Re[3]: impedance across ground plane Todd Hubing
- Re: Re[2]: impedance across ground plane Dr. Edward P. Sayre
- ANTEM'96 Walid Chamma
- Re[4]: impedance across ground plane Tomm V Aldridge
- Re: Re[4]: impedance across ground plane Dr. Edward P. Sayre
- Signal integrity mail list Scott McMorrow
- Vias and decoupling (was Re[x]: impedance across ground plane) Andy Ingraham
- Re: Vias and decoupling (was Re[x]: impedance across ground plane) [email protected]
- drivers, recivers and power planes Larry Smith
- Wanted...PCI bus 3V driver/receiver models Gary Peterson
- Re: Wanted...PCI bus 3V driver/receiver models Ben Andresen
- Re: Wanted...PCI bus 3V driver/receiver models Andy Ingraham
- Re: Wanted...PCI bus 3V driver/receiver models Arthur Collard
- Re[2]: Wanted...PCI bus 3V driver/receiver models Scott McMorrow
- Re[n]: Wanted...PCI bus 3V driver/receiver models Andy Ingraham
- CROSS-TALK Orlando Hernandez
- Job Opening: Beaverton, OR David Boal
- Help John Mladenik
- Ground Bounce? Bradley L. Mendenhall
- Re: Ground Bounce? Greg Edlund
- Ground bounce Mike Jenkins
- Re: Ground Bounce? Don Abernathey
- Re: Ground bounce [email protected]
- Signal Integrity Job:Austin,Texas-Hardware Design Valerie Allen
- Q: SI Course Inputs Brian C. Wadell
- pc board AC noisemap standards George Stevens/UB Networks
- test - please ignore Greg Edlund
- component overstress George Stevens/UB Networks
- Re: component overstress Arthur Collard
- Re: component overstress Greg Edlund
- Re: pc board AC noisemap standards Samie Samaan
- Re: component overstress Arthur Collard
- Re: component overstress Don Abernathey
- Re: pc board AC noisemap standards Don Abernathey
- Comp overstress Gary
- Re: component overstress Andy Ingraham
- Re: component over-stress George Stevens/UB Networks
- Re: component over-stress Arthur Collard
- Signal integrity contract position RodX Strange
- Signal Integrity Job:Austin,Texas-Hardware Design Valerie Allen
- Models for SCSI Ultra Herb Kaupp
- Announcement of Short Course Shirley Dipert
- Modeling for packages (Electrical and thermal). Yehuda D. Yizraeli
- Re: Modeling for packages (Electrical and thermal). Greg Edlund
- Xtalk/Zo tools FABRIZIO ZANELLA
- Re: Xtalk/Zo tools alaa alani
- RE: Xtalk/Zo tools Wojciech Babij/UB Networks
- Re[2]: Xtalk/Zo tools Fabian Wai Lee Kung
- Alloy-42 Steve Majors
- SI- Termination Comments Wa Norman Wong
- Re: SI-Termination Comments Joachim Mueller
- Re: SI- Termination Comments Wa Larry Smith
- Re: Alloy-42 Nirmal Jain
- Re: SI- Termination Comments Wa Bradley L. Mendenhall
- Re: SI- Termination Comments Wa Arpad Muranyi
- Re: Alloy-42 Fred
- Re: SI- Termination Comments Wa [email protected]
- Re: SI- Termination Comment Norman Wong
- Re: SI- Termination Comment Fred
- Re: SI- Termination Comment [email protected]
- Position wanted Mohamed Ouda
- lab electrical requirements Greg Edlund
- Re: lab electrical requirements Jeff Bruce
- Re: lab electrical requirements Don Abernathey
- Signal Integrity Positions Open at Sun Microsystems Ray Anderson
- Who runs NEC under UNIX? Dave Michelson
- Signal Integrity Job:Austin,Texas-Hardware Design Valerie Allen
- CAD Engineer Position Available Ching-Chao Huang
- CAD Engineer Position Ahmed Omer
- Re: limit of method of moments [email protected]
- Re: limit of method of moments Larry Smith
- Limits in MoM calculations Dr. Edward P. Sayre
- Packaging Short Course flyer Shirley Dipert
- Re: Packaging Short Course flyer Don Abernathey
- Buried Capacitance Don Abernathey
- EM Modeling software: What works? Matt, Beverley & McKenzie Oliver
- Re: Buried Capacitance [email protected]
- Buried Capacitance Howard W. Johnson
- FORWARDED from si-admin: Buried Capacitance Ray Anderson
- FORWARDED fro si-admin Re: Buried Capacitance Ray Anderson
- Signal Integrity-Senior Hardware Desing Engineer Valerie Allen
- Junior Hardware Design Engineer Valerie Allen
- Circuit Design Consultant Valerie Allen
- 2 Job Postings Mike A Schmitt
- Re: (Fwd) Buried Capacitance John R Benham
- PCB burried capacitance Larry Smith
- Focussed on USING BC.. Larry Smith
- Schottky Diode terminator SIP packages Scott McMorrow
- Re: Focussed on USING BC.. Larry Smith
- Re:Message for SI List raj mittra
- Schottky Diode terminator SIP packages Howard W. Johnson
- Confer. on wireless comm. Alok Tripathi
- transmission line text Greg Edlund
- Re: transmission line text Larry Smith
- FWD from si-admin: Schottky Diode terminator SIP packages Ray Anderson
- more questions about buried PCB capacitors Eric Bracken
- Re: more questions about buried PCB Al Barber
- Re: more questions about buried PCB capacitors Guang-Tsai Lei
- Re: more questions about buried PCB capacitors Guang-Tsai Lei
- Re: more questions about buried PCB capacitors Guang-Tsai Lei
- Re: PCB burried capacitance Larry Smith
- Program: 1996 Wireless Communications Conference Roger Marks
- Test message . . ignore and delete Ray Anderson
- si-list is alive and well (really) Ray Anderson
- Viewlogic's XTK [email protected]
- FWD: ASIC DESIGNER: case temperture OR ambient temperture...? Ray Anderson
- Ground Plane Info F.Hart
- Re: Ground Plane Info Ahmed Omer
- Re: Ground Plane Info Howard W. Johnson
- Re: Viewlogic's XTK Jonathan Dowling
- Re: Ground Plane Info Frank Yuan
- Differential Pair Skew Don Abernathey
- Differential Pair Skew Howard W. Johnson
- Connectors and cables for high-speed digital signals Per Torstein =?iso-8859-1?Q?R=F8ine?=
- Re: Connectors and cables for high-speed digital signals Tim Nustad x7-4361
- Re: Differential Pair Skew Don Abernathey
- Re: Differential Pair Skew Andy Ingraham
- Re: Differential Pair Skew [email protected]
- Differential Pair Skew F.Hart
- More on Ground Planes F.Hart
- Re: Differential Pair Skew Mike Jenkins
- Re: More on Ground Planes Norman Wong
- Re: Differential Pair Skew Don Abernathey
- Diff Skew Tedd K. Stickel
- Re: Differential Pair Skew Andy Ingraham
- 1GB/s serial Diff Pairs over Backplanes and Connectors Chris Heard/US/3Com
- FWD: Re: More on Ground Planes Ray Anderson
- FWD: Impedance Software Ray Anderson
- Re: Impedance Software [email protected]
- Re: FWD: Impedance Software Richard L. Knapp
- Re: FWD: Impedance Software Richard L. Knapp
- Post articles to si-list NOT si-admin Ray Anderson
- Delete from mailing list Alwyn Goh
- Re: 1GB/s serial Diff Pairs over Backplanes and Connectors Mike Jenkins
- Re: FWD: Impedance Software F.Hart
- Re: Differential Pair Skew Don Abernathey
- Re : Impedance Software Jim Tompkins
- re: Impedance Software Tom Warneke
- re: Impedance Software Tom Warneke
- Re: FWD: Impedance Software FABRIZIO ZANELLA
- Re : Impedance Software Chris Heard/US/3Com
- Re: ASIC DESIGNER: case temperature OR ambient temperature...? ronald de smedt vh41 4650
- Skew, Skew, Differential Skew F.Hart
- SI Software Now Available! brian burke
- Re: FWD: Impedance Software brian burke
- Commercial Postings/Advertising on si-list Ray Anderson
- Position Open Joe Cahill
- Electromechanical relays W. C. Kreiger
- Electromechanical relays W. C. Kreiger
- admin test message Ray Anderson
- pkg elect char job op Wai Yeung Yip
- I/O BUFFER MODELING POSITION Jonathan Dowling
- si-list access down until tommorrow (8-29-96) Ray Anderson
- si-list has returned to operation Ray Anderson
- Modeling - Fast Tr Ray Anderson
- Re: Modeling - Fast Tr Ray Anderson
- Re: Modeling - Fast TR J. Eric Bracken
- Re: Modeling - Fast Tr Richard A. Schumacher
- Re: Modeling - Fast Tr Richard A. Schumacher
- Zeelan Technology Zeelan Technology
- Re: Modeling - Fast Tr Wai Yeung Yip
- Re: Modeling - Fast Tr Fred
- Re: Modeling - Fast Tr Dr. Edward P. Sayre
- Re: Fast TR J. Eric Bracken
- Re: Modeling - Fast Tr Fred
- RE: Modeling - Fast Tr Brian C. Wadell
- Re: Fast TR Richard A. Schumacher
- Re: Fast TR FABRIZIO ZANELLA
- RE: Modeling - Fast Tr Fred
- Re: Modeling - Fast Tr Wai Yeung Yip
- S-parameters and non-linear devices Arpad Muranyi
- Re: S-parameters and non-linear devices Ray Anderson
- well done Roger Gravrok
- Re: S-parameters and non-linear devices Guang-Tsai Lei
- Announcement: si-list server to be off net for several days Ray Anderson
- si-list mail list back on the net. Ray Anderson
- Package charcterization SW, S-I needs etc... Yehuda D. Yizraeli
- Signal Integrity Engineering Position Available at Sun Ray Anderson
- Job Opening at Apple reha.d
- Jobs forum Mary Longtin
- (no subject) Scott Lin
- ISO Bob Canright Russ LeBlanc
- ASSY: GEN: Popcorning during reflow Gary Peterson
- shields Howard Johnson
- MOTIVE Models Don Cummings
- S-Parameter to SPICE Model Converter Rudi ZURBUCHEN
- RE: S-Parameter to SPICE Model Converter Edlund, Greg
- Re: S-Parameter to SPICE Model Converter Ray Anderson
- RE: S-Parameter to SPICE Model Converter Dileep Divekar
- Re: S-Parameter to SPICE Model Converter Rudi ZURBUCHEN
- S-Parameter to SPICE Model Converter Rudi ZURBUCHEN
- Signal integrity opening Robert Voelker
- Ansoft mesh generation Wai Yeung Yip
- Re: Ansoft mesh generation Yehuda D. Yizraeli
- Re: Ansoft mesh generation Gus Panella
- Errata for book: "Digital Circuits Electrical Design" by Ron K. Poon Fred Rosenberger
- Help with decoupling cap inductance Don Abernathey
- (Fwd) Re: Help with decoupling cap inductance Don Abernathey
- Survey of Comp. Electromagnetics Professionals Lloyd Alexander
- (Fwd) Re: Help with decoupling cap inductance Howard Johnson
- New t-line model in Hspice Dmitri Kuznetsov
- SI Engineering Position Farrokh Mottahedin
- Coupled Trans. Line Spice subckt generator program Ray Anderson
- Re: Coupled Trans. Line Spice subckt generator program Ray Anderson
- Coupled Line Program available via anonymous ftp Ray Anderson
- Coupled Line Program available via anonymous ftp Tom Giovannini
- IEEE Workshop "Signal Propagation on Interconnects" Petra Nordholz
- ftp'ing new Hspice's t-line model Dmitri Kuznetsov
- Position Available Terry Morris
- PBGA packaging Arthur Collard
- Re: PBGA packaging Larry Smith
- Please add me to your mailing list. eli leshem
- Board-Level Design Engineer Position at Silicon Graphics Heinz Blennemann
- IBIS Models or full spice netlist...? Yehuda D. Yizraeli
- re: IBIS Models or full spice netlist...? Howard Johnson
- Re: IBIS Models or full spice netlist...? Fred
- Re: IBIS Models or full spice netlist...? Heinz Blennemann
- Re: IBIS Models or full spice netlist...? Gus Panella
- Re: IBIS Models or full spice netlist...? C. Kumar
- Re: IBIS Models or full spice netlist...? Bob Penick
- Re: IBIS Models or full spice netlist...? Jon Powell
- Unsubscribe from reflector Bob Reed
- Board-Level Design Engineer Position at Silicon Graphics Heinz Blennemann
- Signal Integrity advertisement Steve Krenitsky
- FCT806 Clock Driver fabrizio zanella
- FCT806 Clock Driver Gary Peterson
- Re: FCT806 Clock Driver [email protected]
- Re: FCT806 Clock Driver Norman Wong
- RE: FCT806 Clock Driver [email protected]
- Re: RE: FCT806 Clock Driver Richard Evans
- SI job opportunity in Intel Santa Clara Chris Cheng
- SI positions available at Compaq [email protected]
- SIGNAL INTEGRITY ENG. OPENING BREMER, ROBERT WH:3821
- Design Engineers wanted in Pacific NW! the shadow
- Re: Design Engineers wanted in Pacific NW! Ray Anderson
- Call for Papers - IEEE ISIS'97 Ahmed Omer
- Signal Integrity position available Joe Cahill
- Joint Technical Societies, Nepcon West, L.A. Area Bill Gaines B160 x2199
- SI job opportunity at Intel's DuPont, Washington facitlity! John Zavertnik
- Inductance calculation Eric Wheatley
- Re: Inductance calculation Mike Jenkins
- Re: Inductance calculation Sandy Taylor
- Inductance calculation Howard Johnson
- L/R response time Edlund, Greg
- Re: Inductance calculation Uwe Keller
- Re: L/R response time Uwe Keller
- Re: L/R response time J. Eric Bracken
- Re: L/R response time Andy Ingraham 18-Feb-1997 1154
- Re: decoupling/ bypass capacitors at connectors Howard Johnson
- Dual Stripline Walt Kreiger
- Re: decoupling/ bypass capacitors at connectors Larry Smith
- Re: decoupling/ bypass capacitors at connectors [email protected]
- Re: Dual Stripline [email protected]
- Re: decoupling/ bypass capacitors at connectors [email protected]
- Re: decoupling/ bypass capacitors at connectors Larry Smith
- Re: decoupling/ bypass capacitors at connectors Dr. Edward P. Sayre
- Re: decoupling/ bypass capacitors at connectors [email protected]
- Re: decoupling/ bypass capacitors at connectors Larry Smith
- Re: decoupling/ bypass capacitors at connectors Doug Brooks
- Silicon Circuit Design for High Speed and Low Power [email protected]
- Silicon Circuit Design for High Speed [email protected]
- via clearance question John Lipsius
- Spice to IBIS ELUZ YAACOV 9115/9 608 3467 362/7-s100_5
- Spice to IBIS ELUZ YAACOV 9115/9 608 3467 362/7-s100_5
- Re: Spice to IBIS Yehuda D. Yizraeli
- IMAPS Orange Chapter March meeting L.A. Area Bill Gaines B160 x2199
- Public SI Seminar Howard Johnson
- Re: Public SI Seminar Andy Ingraham
- IEEE Workshop "Signal Propagation on Interconnects" [email protected]
- Controlled Impedance Connectors Colin Campbell
- Re: Controlled Impedance Connectors [email protected]
- Re: Controlled Impedance Connectors Simon Amir - SMCC Desktop
- Separate +5V Plane Farrokh Mottahedin
- Re: Separate +5V Plane [email protected]
- Dual stripline Walt Kreiger
- RE: Separate +5V Plane Grasso, Charles
- Re: Separate +5V Plane Andy Ingraham
- Ansoft Seminar Series this week Eric Bogatin
- vias in ECL @ >1Ghz Jeff Seeger
- Re: vias in ECL @ >1Ghz J. Eric Bracken
- Re: vias in ECL @ >1Ghz [email protected]
- Re: vias in ECL @ >1Ghz Don Abernathey
- Module Hardware Design Engineer positions Michael Chin
- Re: vias in ECL @ >1Ghz Xingchao Yuan
- Re: vias in ECL @ >1Ghz Tom Giovannini
- RE: Re: vias in ECL @ >1Ghz [email protected]
- split plane/micro-island [email protected]
- Help/cross-talk guidelines Doug Brooks
- RE: Help/cross-talk guidelines Andy Ingraham
- New t-line model in Hspice Dmitri Kuznetsov
- Differential clock fabrizio zanella
- Line Parameters of Twisted Cables ? Dr. Bardo Mueller
- RE: Line Parameters of Twisted Cables ? Brian C. Wadell
- RE: Differential clock Edlund, Greg
- differential impedance Weston Beal
- Re: Line Parameters of Twisted Cables ? Tom Warneke
- Re: Line Parameters of Twisted Cables ? Weston Beal
- differential impedance F.Hart
- Re: differential impedance J. Eric Bracken
- New t-line model in Hspice Joe Cahill
- re: Help/cross-talk guidelines fabrizio zanella
- Re: differential impedance Eric Wheatley
- Re: Line Parameters of twisted cables [email protected]
- IMAPS Orange Chapter April Meeting L.A. Area Bill Gaines B160 x2199
- Resume Ki Hong Kim
- FAQ request Gus Panella
- Differential Impedance Dr. Edward P. Sayre
- Re: Differential Impedance [email protected]
- Line Parameters of Twisted Cables ? Dr. Bardo Mueller
- Line Parameters of Twisted Cables ? Dr. Bardo Mueller
- Re: differential impedance Fred
- Example ECL driver/receiver model Mayura Ladwa
- Re: Example ECL driver/receiver model Zeelan Technology
- Re: Differential clock Howard Johnson
- ASIC Design Positions @ Packet Engines!!! Dave Roth
- Signal Integrity Applications Engineer Harris, Stanley
- animation program to show travelling wave johnlin
- re:animation program to show travelling wave Norman Wong
- Re: animation program to show travelling wave Farrokh Mottahedin
- Re: animation program to show travelling wave Danwei Xue
- re:animation program to show travelling wave John Fessler
- Re: animation program to show travelling wave Dmitri Kuznetsov
- Re: animation program to show travelling wave Don Abernathey
- Re: animation program to show travelling wave Bill Gaines B160 x2199
- Open position Myoung Jin
- Positions available Ching-Chao Huang
- animation program to show travelling wave [email protected]
- SI engineers wanted Ellis, John R
- ATM positions in Dallas Saurabh Tewari
- Re: ATM positions in Dallas Michael Nagel
- FW: SI engineers wanted - address correction Ellis, John R
- Power/ground connections/bypassing on ICs Andy Ingraham
- Re: Power/ground connections/bypassing on ICs Larry Smith
- Re: Power/ground connections/bypassing on ICs [email protected]
- Re: Power/ground connections/bypassing on ICs Michael Nagel
- Re: Power/ground connections/bypassing on ICs Gary Peterson
- Re: Power/ground connections/bypassing on ICs Larry Smith
- Re: Power/ground connections/bypassing on ICs Bob Techentin
- Re: Power/ground connections/bypassing on ICs Larry Smith
- Re: Power/ground connections/bypassing on ICs Don Abernathey
- Formula for Via Self-Capacitance and Self-Inductance Tat Hin Tan
- Re: Power/ground connections/bypassing on ICs Andy Ingraham
- math sw for Unix??? John Lipsius
- RE: Power/ground connections/bypassing on ICs Clardy, John D
- Re: math sw for Unix??? Uwe Keller
- Re: Power/ground connections/bypassing on ICs Andy Ingraham
- temporary si-list outage Ray Anderson
- Re: did you receive this via si-list ?? Larry Smith
- Re: Power/ground connections/bypassing on ICs Mark Randol
- Re: Power/ground connections/bypassing on ICs Howard Johnson
- participation on the SI group Seung Ho Hwang
- guide line of PCB placement to reduce EMI/SI problem John Lin
- re:guide line of PCB placement to reduce EMI/SI problem Norman Wong
- RE: Power/ground connections/bypassing on ICs Grasso, Charles
- continously variable delay line avail? John Lipsius
- Re: continously variable delay line avail? [email protected]
- Delay line Csaba Csaszar
- RE: continously variable delay line avail? [email protected]
- Re: Power/ground connections/bypassing on ICs Larry Smith
- traces as antennas Pete Waddell
- Looking for Signal Integrity Engineer Steven Ray
- need help for networking loop back, Thanks John Lin - TAO
- R: need help for networking loop back, Thanks [email protected]
- need help for networking loop back, Thanks John Lin - TAO
- Networking loop back -- Please use my email address instead of replying button John Lin - TAO
- Re: need help for networking loop back, Thanks Andy Ingraham 28-May-1997 0740
- Twisted pair cables Cary Mandel
- RE: Twisted pair cables Mellitz, Richard
- What is SSTL? Danwei Xue
- Re: Pullup resistors on 3-state buses Andy Ingraham
- Re: What is SSTL? fabrizio zanella
- Pullup resistors on 3-state buses John V Fitzpatrick
- Re: What is SSTL? John V Fitzpatrick
- Re: Pullup resistors on 3-state buses Bob Davis
- s2ibis questions Tim McKinney
- s2ibis questions Tim McKinney
- s2ibis questions Syed Huq
- [Fwd: Interfacing Sync DRAMs] Danwei Xue
- Inter-Symbol Interference Farrokh Mottahedin
- RE: Inter-Symbol Interference Edlund, Greg
- Re: Inter-Symbol Interference Jon Powell
- re: intersymbol Interference Del Cecchi
- Re: Inter-Symbol Interference Mike Jenkins
- Vertical Transmission Line ... Geraldo Peres Caixeta
- Re: Vertical Transmission Line ... Uwe Keller
- reactance of 0805 and smaller SMT resistors? preferred suppliers? John Nieznanski
- Re: reactance of 0805 and smaller SMT resistors? preferred suppliers? Ray Anderson
- reactance of 0805 and smaller SMT resistors? preferred suppliers? Larry Miller
- reactance of 0805 and smaller SMT resistors Charles Hill
- reactance of 0805 and smaller SMT resistors Howard Johnson
- Re: reactance of 0805 and smaller SMT resistors Mark Randol
- Re: reactance of 0805 and smaller SMT resistors Eric Wheatley
- FW: reactance of 0805 and smaller SMT resistors Edlund, Greg
- Re: FW: reactance of 0805 and smaller SMT resistors J. Eric Bracken
- Re: FW: reactance of 0805 and smaller SMT resistors [email protected]
- Partial Inductance - NOT L D Miller
- Thermal Relief Design [email protected]
- Thanks Re: Pullup resistors on 3-state buses John V Fitzpatrick
- Re: Thermal Relief Design Farrokh Mottahedin
- Re: Partial Inductance J. Eric Bracken
- Re: Thermal Relief Design Jeff Seeger
- RE: Partial Inductance Edlund, Greg
- RE: Partial Inductance Larry Rubin
- RE: Partial Inductance (correction) Larry Rubin
- Re: FW: reactance of 0805 and smaller SMT resistors Charles Hill
- Vcc power planes Bradley L. Mendenhall
- RE: Vcc power planes Grasso, Charles
- Electrical Package Characterization Engineer Nozad Karim
- PSI Connector impedances Grasso, Charles
- Shielding Sean Murray
- Re: Shielding/ Guardbanding Heinz Blennemann
- RE: Shielding Peterson, James F
- Re: Shielding Andy Ingraham
- RE: Shielding Grasso, Charles
- Re: Shielding [email protected]
- Re: Shielding [email protected]
- Re: Shielding Fred
- guard traces. Alok Tripathi
- Formulas for Crosstalk Calculation PCB traces Hans Ziegler
- re: Formulas for Crosstalk Calculation PCB traces [email protected]
- The Criteria of overshoot, undershoot, RingBack for different logic types John Lin - TAO
- Re: Formulas for Crosstalk Calculation PCB traces Eric Bogatin
- +3.3,5-board stackup problem Stuart P. MacEachern
- Re: +3.3,5-board stackup problem Ravinder Ajmani
- Re: +3.3,5-board stackup problem Mike Jenkins
- Re: +3.3,5-board stackup problem / return currents... Jeff Seeger
- Re: +3.3,5-board stackup problem / return currents... Larry Smith
- Radiation Losses of Transmission Lines Dr. Bardo Mueller
- Re: The Criteria of overshoot, undershoot, RingBack for Karthik Ethirajan
- IBIS 3.0 Gary Oehrle
- Re: IBIS 3.0 Bob Ross
- resend the question. please answer to my fully E-mail address John Lin - TAO
- Radiation Losses of Transmission Lines Dr. Bardo Mueller
- Re: resend the question. (The Criteria of overshoot, undershoot, RingBack for different logic types Andy Ingraham
- Re: resend the question. (The CGround plane on top layer? Anthony Tse
- ibis 3.0 Karthigeyan Ranganathan
- Signaling Technologies Marc Jensen
- si-list archives now available on the world wide web !!! [email protected]
- RE: resend the question. (The Criteria of overshoot, undershoot, RingBack for different logic types Andy Ingraham
- RE: resend the question. (The Criteria of overshoot, undershoot, RingBack for different logic types John Lin - TAO
- Relative Permeability and Resistivity of Eutectic Solder Ball Yee Pak Hong
- Relative Permeability and Resistivity of Eutectic Solder Ball Yee Pak Hong
- Simultaneous Switching alaa alani
- Newbie question Re: PCB SI simulation tools Brett Grossman
- Re: Simultaneous Switching and differential buffer skew Joe Cahill
- Spice model for PCI driver Hans Ziegler
- Re: Newbie question Re: PCB SI simulation tools [email protected]
- Re: Relative Permeability and Resistivity of Eutectic Solder Ball Tim Postel
- Re: Newbie question Re: PCB SI simulation tools Uwe Keller
- Relative Permeability and Resistivity of Eutectic Solder Ball Yee Pak Hong
- Relative Permeability and Resistivity of Eutectic Solder Ball Yee Pak Hong
- Spice model for PCI driver Hans Ziegler
- Simultaneous Switching alaa alani
- Re: Relative Permeability and Resistivity of Eutectic Solder Ball Tim Postel
- Newbie question Re: PCB SI simulation tools Brett Grossman
- SI-LIST now Automated Ray Anderson
- Connector pinout question Paul Thompson
- Re: SPICE model for PCI driver Michael Flint
- Archive required Csaba Csaszar
- RE: resend the question. (The Criteria of overshoot, undershoot, RingBack for different logic types Andy Ingraham
- Need info on BGA packages Andrew Phillips
- 3.3V/5V planes fabrizio zanella
- RE: 3.3V/5V planes Peterson, James F
- Re: 3.3V/5V planes Jeff Seeger
- si-list RE: 3.3V/5V planes Bremer, Robert
- [SI-LIST] : Ground bouncing ??? John Lin - TAO
- [SI-LIST] : Clock chip supply voltage Kazi Hassan
- Re: [SI-LIST] : Ground bouncing ??? Jose Luis Gonzalez Jimenez
- Re: [SI-LIST] : Clock chip supply voltage [email protected]
- [SI-LIST] : Re: Connector pinout question Andy Ingraham
- Re: [SI-LIST] : Clock chip supply voltage Kazi Hassan
- [SI-LIST] : Backplane Analysis / GTL Technology Jim McNamara
- Re: [SI-LIST] : Backplane Analysis / GTL Technology Karthik Ethirajan
- [SI-LIST] : Reliability Forums [email protected]
- Re: [SI-LIST] : Backplane Analysis / GTL Technology JOHN HANS-JOERG
- Re: [SI-LIST] : Backplane Analysis / GTL Technology Ramzi Ammar
- [SI-LIST] : TDR formula Kihong Kim
- Re: [SI-LIST] : Backplane Analysis / GTL Technology Shankar
- [SI-LIST] : BackPlane stackup John Lin - TAO
- Re: [SI-LIST] : BackPlane stackup Chris Heard/US/3Com
- Re: [SI-LIST] : TDR formula Dr. Edward P. Sayre
- [SI-LIST] : Buried Capacitors Dr. Edward P. Sayre
- Re: [SI-LIST] : TDR formula Mike Jenkins
- Re: [SI-LIST] : Buried Capacitors Larry Smith
- Re: [SI-LIST] : Buried Capacitors Paul Franzon
- Re: [SI-LIST] : Buried Capacitors Ravinder Ajmani
- Re: [SI-LIST] : Buried Capacitors Ray Anderson
- [SI-LIST] : TDR formula Kihong Kim
- [SI-LIST] : Digital Interconnect Position at HP Al Barber
- [SI-LIST] : Multi-wire boards Peterson, James F
- [SI-LIST] : High freq. mag. prop. of Kovar Eric Wheatley
- [SI-LIST] : Power/ground plane models Raymond Chen
- Re: [SI-LIST] : Power/ground plane models Larry Smith
- Re: [SI-LIST] : Power/ground plane models Larry Smith
- [SI-LIST] : Test Message (delete before reading:) Ray Anderson
- [SI-LIST] : 2 great Signal Fidelity positions open at Stratus!!! [email protected]
- [SI-LIST] : "Bob Smith" Termination Ellis, John R
- Re: [SI-LIST] : "Bob Smith" Termination L D Miller
- Re: [SI-LIST] : "Bob Smith" Termination Jim Lyke
- [SI-LIST] : Test Message (delete before reading:) Tedd K. Stickel
- [SI-LIST] : Teaching SI Melinda Piket-May
- Re: [SI-LIST] : Teaching SI Karthik Ethirajan
- Re: [SI-LIST] : Teaching SI Fethi Bellamine
- Re: [SI-LIST] : Teaching SI Ray Anderson
- Re: [SI-LIST] : Teaching SI [email protected]
- Re: [SI-LIST] : Teaching SI Ron Poon
- [SI-LIST] : Speaker sought [email protected]
- [SI-LIST] : Electrical Package Characterization Engineer Nozad Karim
- Re: [SI-LIST] : Teaching SI Fethi Bellamine
- [SI-LIST] : software development position at Cadence Kenneth Willis
- [SI-LIST] : PCB Bennchmark '98 Pete Waddell
- [SI-LIST] : PCB Benchmark '98 Pete Waddell
- [SI-LIST] : PCB Benchmark '98 Pete Waddell
- [SI-LIST] : PCB Benchmark '98 Larry Smith
- [SI-LIST] : PLD/FPGA folks Pete Waddell
- Re: [SI-LIST] : Digital Interconnect Position at HP Neven Orhanovic
- Re: [SI-LIST] : Digital Interconnect Position at HP Neven Orhanovic
- [SI-LIST] : SSO in ASICs John V Fitzpatrick
- Re: [SI-LIST] : SSO in ASICs [email protected]
- Re: [SI-LIST] : SSO in ASICs [email protected]
- Re: [SI-LIST] : SSO in ASICs Robert Tsai
- [SI-LIST] : Eastern IBIS Kickoff Meeting Sept 18 Dr. Edward P. Sayre
- Re: [SI-LIST] : Eastern IBIS Kickoff Meeting Sept 18 Arpad Muranyi
- Re: [SI-LIST] : SSO in ASICs Mike Mayer
- [SI-LIST] : Rev -1 Eastern IBIS Kickoff Meeting Sept 18 Dr. Edward P. Sayre
- RE: [SI-LIST] : SSO in ASICs Edlund, Greg
- re: [SI-LIST] : Eastern IBIS Kickoff Meeting Sept 18 fabrizio zanella
- [SI-LIST] : IBIS Meeting September 18th Haruny Said
- Re: [SI-LIST] : Regular Full-time Technical Positions Dr. Edward P. Sayre
- RE: [SI-LIST] : Regular Full-time Technical Positions Peterson, James F
- RE: [SI-LIST] : Regular Full-time Technical Positions L D Miller
- RE: [SI-LIST] : Regular Full-time Technical Positions Grasso, Charles
- RE: [SI-LIST] : Regular Full-time Technical Positions Doug Brooks
- Re: [SI-LIST] : Regular Full-time Technical Positions [email protected]
- Re: [SI-LIST] : Regular Full-time Technical Positions [email protected]
- [SI-LIST] : Apology Shawn Drumgo
- [SI-LIST] : PCB Build Vince Harradine
- Re: [SI-LIST] : PCB Build L D Miller
- [SI-LIST] : An update on the IBIS East meeting for 18 September, 1997 Dr. Edward P. Sayre
- [SI-LIST] : Output driver versus internal logic switching noise Jose Luis Gonzalez Jimenez
- Re: [SI-LIST] : Output driver versus internal logic switching noise Arthur Collard
- [SI-LIST] : Mass: Signal Integrity/Timing 6+ Month Contract Don Cummings
- Re: [SI-LIST] : Output driver versus internal logic switching noise Larry Smith
- RE: [SI-LIST] : Output driver versus internal logic switching noise Peterson, James F
- Re: [SI-LIST] : PCB Build Diane A. Delute
- [SI-LIST] : need accurate diode model at low current [email protected]
- [SI-LIST] : Opening at Dell Frances Hart
- Re: [SI-LIST] : Output driver versus internal logic switching noise Andy Ingraham
- [SI-LIST] : skin effect and transmission line simulators Chris Simon
- [SI-LIST] : skin effect and transmission line simulators Chris Simon
- Re: [SI-LIST] : skin effect and transmission line simulators Ray Anderson
- Re: [SI-LIST] : skin effect and transmission line simulators Eric B. Lewis
- [SI-LIST] : signal level conversions Eric N. Lewis
- [SI-LIST] : Dispersive interconnects and skin effect Andreas Cangellaris
- Re: [SI-LIST] : skin effect and transmission line simulators Larry Rubin
- Re: [SI-LIST] : skin effect and transmission line simulators Al Barber
- Re: [SI-LIST] : skin effect and transmission line simulators J. Eric Bracken
- [SI-LIST] : IBIS model question Peterson, James F
- Re: [SI-LIST] : skin effect and transmission line simulators Russ
- Re: [SI-LIST] : IBIS model question Andy Ingraham
- [SI-LIST] : SI Software Mike Mayer
- Re: [SI-LIST] : skin effect and transmission line simulators [email protected]
- Re: [SI-LIST] : SI Software Tom Warneke
- Re: [SI-LIST] : SI Software Roland F. Portman
- [SI-LIST] : IBIS model question Peterson, James F
- Re: [SI-LIST] : skin effect and transmission line simulators Jonathan Smith
- Re: [SI-LIST] : skin effect and transmission line simulators Dmitri Kuznetsov
- Re: [SI-LIST] : skin effect and transmission line simulators Syed Huq
- [SI-LIST] : Skin effect Modeling and Verification Dr. Edward P. Sayre
- RE: [SI-LIST] : Skin effect Modeling and Verification Mellitz, Richard
- Re: [SI-LIST] : skin effect and transmission line simulators fabrizio zanella
- [SI-LIST] : Challenging Signal Integrity Engineer Positions @ Stratus! [email protected]
- [SI-LIST] : EPEP'97 ADVANCED PROGRAM Alina Deutsch
- [SI-LIST] : call for papers - PCB West Pete Waddell
- Re: [SI-LIST] : skin effect and transmission line simulators Dr. Edward P. Sayre
- Re: [SI-LIST] : skin effect and transmission line simulators Torsten Maeser
- RE: [SI-LIST] : skin effect and transmission line simulators Mellitz, Richard
- [SI-LIST] : Dinner mtg 26sept97, Los Angeles area Bill Gaines B160 x2199
- [SI-LIST] : 9/18/97 - IBIS FORUM - EAST Agenda & Directions Kathy Breda
- [SI-LIST] : Test Message (delete before reading:) Ray Anderson
- [SI-LIST] : UltraCAD needs another designer Doug Brooks
- [SI-LIST] : Re:Dinner mtg 26sept97 s/b25th Bill Gaines B160 x2199
- [SI-LIST] : Horror stories ? Roger Gravrok
- [SI-LIST] : Books Mellitz, Richard
- Re: [SI-LIST] : Books Karen Potvin
- Re: [SI-LIST] : Books Jon Burnett
- Re: [SI-LIST] : Books Jon Burnett
- [SI-LIST] : Books [email protected]
- [SI-LIST] : Books (Montrose, Johnson) Lisa Schaertl
- [SI-LIST] : Burst noise simulation Unger Bernhard
- Re: [SI-LIST] : Burst noise simulation John Nguyen
- [SI-LIST] : Books Doug Brooks
- [SI-LIST] : Book for sale Todd Nichols
- [SI-LIST] : Open positions at MCNC Paul Franzon
- [SI-LIST] : Signal Integrity Engineering opportuinities at Intel Corp. RhondaX Rutledge
- Re: [SI-LIST] : Burst noise simulation [email protected]
- [SI-LIST] : stackup impedance. John Lin - TAO
- [SI-LIST] : �^�� : [SI-LIST] : stackup impedance. Weber Chuang
- Re: [SI-LIST] : stackup impedance. Andy Ingraham
- Re: [SI-LIST] : (unknown chars) : [SI-LIST] : stackup impedance. [email protected]
- Re: [SI-LIST] : stackup impedance. [email protected]
- Re: [SI-LIST] : �^�� : [SI-LIST] : stackup impedance. Ron Bader
- Re: [SI-LIST] : stackup impedance. Eric Bogatin
- [SI-LIST] : differential pairs Joachim Mueller
- Re: [SI-LIST] : differential pairs Ron Poon
- [SI-LIST] : differential pairs [email protected]
- Re: [SI-LIST] : differential pairs Mike Jenkins
- Re: [SI-LIST] : stackup impedance. Torsten Maeser
- Re: [SI-LIST] : stackup impedance. Andy Ingraham
- Re: [SI-LIST] : differential pairs Andy Ingraham
- [SI-LIST] : AMPredictor Michael Allen
- Re: [SI-LIST] : Burst noise simulation Torsten Maeser
- Re: [SI-LIST] : stackup impedance. Joachim Mueller
- Re: [SI-LIST] : stackup impedance. Joachim Mueller
- RE: [SI-LIST] : skin effect and transmission line simulators Clardy, John D
- [SI-LIST] : Dielectric loss [email protected]
- Re: [SI-LIST] : Dielectric loss Nirmal Jain
- [SI-LIST] : Transmission Line Conductors Alastair Hardie
- Re: [SI-LIST] : Transmission Line Conductors [email protected]
- [SI-LIST] : Re: Dielectric loss Neven Orhanovic
- [SI-LIST] : �^�� : [SI-LIST] : stackup impedance. Weber Chuang
- Re: [SI-LIST] : Transmission Line Conductors [email protected]
- [SI-LIST] : [SI-LIST]:Re: dielectric loss Vadim Heyfitch
- Re: [SI-LIST] : PCB parameters Chris Heard/US/3Com
- Re: [SI-LIST] : PCB parameters fabrizio zanella
- AW: [SI-LIST] : Burst noise simulation Unger Bernhard
- Re: AW: [SI-LIST] : Burst noise simulation [email protected]
- FW: [SI-LIST] : Dielectric loss (Intuitive explanation) Hemant Shah
- [SI-LIST] : Single-ended SCSI vs. differential SCSI [email protected]
- [SI-LIST] : Transmission Line Conductors Alastair Hardie
- [SI-LIST] : Single-ended SCSI vs. differential SCSI [email protected]
- RE: [SI-LIST] : Single-ended SCSI vs. di [email protected]
- [SI-LIST] : Re: Transmission Line Conductors [email protected]
- Re: [SI-LIST] : Transmission Line Conductors Richard Wheeler
- Re: [SI-LIST] : Single-ended SCSI vs. di Fred Townsend
- Re: [SI-LIST] : skin effect and transmission line simulators Jamie Metcalfe
- RE: [SI-LIST] : Transmission Line Conductors Brian C. Wadell
- [SI-LIST] : resistor models Andrew Phillips
- AW: AW: [SI-LIST] : Burst noise simulation Unger Bernhard
- [SI-LIST] : [SI-LIST]:S,R,Z, I logic states Eric B. Lewis
- [SI-LIST] : PCB track length and ringing Gopala Krishna M.R.
- [SI-LIST] : Formulas for Calculating PTH Capacitance Chris Heard/US/3Com
- Re: [SI-LIST] : PCB track length and ringing [email protected]
- Re: [SI-LIST] : Formulas for Calculating PTH Capacitance Mike Jenkins
- re: [SI-LIST] : Formulas for Calculating PTH Capacitance fabrizio zanella
- Re: [SI-LIST] : PCB track length and ringing Danwei Xue
- Re: [SI-LIST] : PCB track length and ringing Danwei Xue
- Re: [SI-LIST] : PCB track length and ringing Karthik Ethirajan
- [SI-LIST] : Net topology, reflection cancellation ? John Lin - TAO
- [SI-LIST] : Career Opportunity Mike Fleice [CONTRACTOR]
- Re: [SI-LIST] : PCB track length and ringing Larry Smith
- Re: [SI-LIST] : PCB track length and ringing [email protected]
- Re: [SI-LIST] : PCB track length and ringing [email protected]
- [SI-LIST] : delay lines Ray Anderson
- Re: [SI-LIST] : delay lines Andy Ingraham
- [SI-LIST] : delay lines [email protected]
- Re: [SI-LIST] : PCB track length and ringing Arthur Collard
- [SI-LIST] : Re: delay lines with PCB traces Michael Chin
- Re: [SI-LIST] : Re: delay lines with PCB traces Brett Grossman
- Re: [SI-LIST] : PCB track length and ringing Dmitri Kuznetsov
- [SI-LIST] : Re: delay lines with PCB traces Paul Galloway
- [SI-LIST] : Re: delay lines with PCB traces Michael Chin
- [SI-LIST] : SSO noise: Through current vs. Discharge current John V Fitzpatrick
- Re: [SI-LIST] : Re: delay lines with PCB traces Xingchao Yuan
- Re: [SI-LIST] : Re: delay lines with PCB traces Bob Techentin
- Re: [SI-LIST] : PCB track length and ringing Larry Smith
- Re: [SI-LIST] : Re: delay lines with PCB traces Xingchao Yuan
- Re: [SI-LIST] : Re: delay lines with PCB traces Mark McKee
- RE: [SI-LIST] : SSO noise: Through current vs. Discharge current Peterson, James F
- RE: [SI-LIST] : Re: delay lines with PCB traces Mellitz, Richard
- [SI-LIST] : Re: delay lines with PCB traces Ryszard Vogel
- [SI-LIST] : Schiffman phase shifters Dr. Edward P. Sayre
- Re: [SI-LIST] : Schiffman phase shifters Doug Day
- [SI-LIST] : W-element Simulation Doug Day
- Re: [SI-LIST] : SSO noise: Through current vs. Discharge current Jose Luis Gonzalez Jimenez
- [SI-LIST] : Re: [SI-LIST]: SSO noise: Through current vs. Discharge current] Michael Gutzmann
- [SI-LIST] : Pinout of 2mm HM Backplane Connector WonSae Sim
- Re: [SI-LIST] : Schiffman phase shifters Richard A. Schumacher
- Re: [SI-LIST] : W-element Simulation Dmitri Kuznetsov
- Re: [SI-LIST] : Schiffman phase shifters Brett Grossman
- Re: [SI-LIST] : stackup impedance. Doug Brooks
- Re: [SI-LIST] : SSO noise: Through current vs. Discharge current Jose Luis Gonzalez Jimenez
- [SI-LIST] : UltraCAD needs 2 designers Doug Brooks
- [SI-LIST] : si-list archive temporarily unavailable Ray Anderson
- [SI-LIST] : Can floating data bus cause DRAM soft errors? John V Fitzpatrick
- Re: [SI-LIST] : Can floating data bus cause DRAM soft errors? Mike Mayer
- Re: [SI-LIST] : Can floating data bus cause DRAM soft errors? L D Miller
- [SI-LIST] : bare board resonance test [email protected]
- Re: [SI-LIST] : bare board resonance test [email protected]
- [SI-LIST] : Minutes from IBIS-East Forum kickoff meeting Kathy Breda
- [SI-LIST] : Package prices and circuit elements values Jose Luis Gonzalez Jimenez
- Re: [SI-LIST] : Package prices and circuit elements values Brett Grossman
- [SI-LIST] : EUROPE IBIS SUMMIT MEETING Bob Ross
- [SI-LIST] : EDA suite for Win NT Russell Rapport
- [SI-LIST] : SI Consulting Opportunity in Silicon Valley Ray Anderson
- [SI-LIST] : Confidential Search for Sr Signal Integrity Engineer Gary Fowler
- Re: [SI-LIST] : SI Consulting Opportunity in Silicon Valley [email protected]
- [SI-LIST] : Standard PCI load Rick Tan
- [SI-LIST] : Board Stack-up Peterson, James F
- [SI-LIST] : CALL FOR PAPERS, 2nd International Workshop on SIGNAL Treytnar Dieter
- Re: [SI-LIST] : Board Stack-up Andrew Ingraham
- [SI-LIST] : more on pcb stack-ups Peterson, James F
- Re: [SI-LIST] : more on pcb stack-ups Andrew Ingraham
- [SI-LIST] : Package design position Paul Y.F. Wu
- [SI-LIST] : Authors Wanted Ronda Faries
- [SI-LIST] : Great Opportunity @Sun Mike Fleice [CONTRACTOR]
- [SI-LIST] : Decoupling capacitor selection & placement Andrew Phillips
- [SI-LIST] : Decoupling capacitor selection & placement Gopala Krishna M.R.
- [SI-LIST] : EMI Manix Velu
- Re: [SI-LIST] : Decoupling capacitor selection & placement Fred Townsend
- Re: [SI-LIST] : EMI Scott McMorrow
- Re: [SI-LIST] : Decoupling capacitor selection & placement Michael Nagel
- Re[2]: [SI-LIST] : Decoupling capacitor selection & placemen [email protected]
- Re: [SI-LIST] : EMI [email protected]
- [SI-LIST] : Cautious offer to test.... [email protected]
- Re: [SI-LIST] : Decoupling capacitor selection & placement D. C. Sessions
- [SI-LIST] : Ansoft SI seminar coming soon Eric Bogatin
- Re: [SI-LIST] : Decoupling capacitor selection & placemen D. C. Sessions
- [SI-LIST] : EMI [email protected]
- RE: [SI-LIST] : EMI Grasso, Charles
- Re: [SI-LIST] : Decoupling capacitor selection & placement Brett Grossman
- Re: [SI-LIST] : EMI [email protected]
- [SI-LIST] : EMI Kelly McClellan x2393
- [SI-LIST] : Decoupling Caps and Return Currents Mark Nass
- [SI-LIST] : Modeling connector pin vias [email protected]
- Re: [SI-LIST] : Modeling connector pin vias Chris Heard/US/3Com
- [SI-LIST] : Excellent Reference Book Ron Bader
- Re: [SI-LIST] : Modeling connector pin vias Dr. Edward P. Sayre
- Re: [SI-LIST] : EMI Dr. Edward P. Sayre
- Re: Re[2]: [SI-LIST] : Decoupling capacitor selection & placemen Anders Ekholm
- Re: [SI-LIST] : Modeling connector pin vias Mike Jenkins
- Re[4]: [SI-LIST] : Decoupling capacitor selection & plac [email protected]
- Re: Re[4]: [SI-LIST] : Decoupling capacitor selection & plac Bob Techentin
- [SI-LIST] : FW: SI Engineer position Lam, Son H
- Re: [SI-LIST] : Modeling connector pin vias Tat Hin Tan
- Re: [SI-LIST] : EMI [email protected]
- Re: Re[2]: [SI-LIST] : Decoupling capacitor selection & plac Ravinder Ajmani
- Re: [SI-LIST] : EMI [email protected]
- Re: [SI-LIST] : EMI [email protected]
- Re: [SI-LIST] : EMI Neven Orhanovic
- [SI-LIST] : low-cost 2-D field solver Greg Edlund
- Re: [SI-LIST] : Decoupling capacitor selection & placement D. C. Sessions
- Re: [SI-LIST] : Decoupling capacitor selection & placement D. C. Sessions
- Re: [SI-LIST] : low-cost 2-D field solver Tat Hin Tan
- Re: [SI-LIST] : low-cost 2-D field solver Tat Hin Tan
- Re: [SI-LIST] : Modeling connector pin vias Tat Hin Tan
- [SI-LIST] : Signal Integrity of 500 MHz on PCB [email protected]
- RE: Re[2]: [SI-LIST] : Decoupling capacitor selection & plac Peterson, James F
- Re: [SI-LIST] : Signal Integrity of 500 MHz on PCB Fred Townsend
- Re: [SI-LIST] : Signal Integrity of 500 MHz on PCB Mike Jenkins
- Re: [SI-LIST] : Signal Integrity of 500 MHz on PCB [email protected]
- RE: Re[2]: [SI-LIST] : Decoupling capacitor selection & pl [email protected]
- Re: [SI-LIST] : Signal Integrity of 500 MHz on PCB D. C. Sessions
- RE: [SI-LIST] : Decoupling capacitor selection & placemen Mellitz, Richard
- Re: [SI-LIST] : Decoupling capacitor selection & placemen D. C. Sessions
- RE: Re[2]: [SI-LIST] : Decoupling capacitor selection & plac Dr. Edward P. Sayre
- Re: [SI-LIST] : Decoupling capacitor selection & placemen Paul Galloway
- [SI-LIST] : Stratus looking for Signal Fidelity Engineers [email protected]
- Re: [SI-LIST] : Signal Integrity of 500 MHz on PCB Katja Zuleeg
- [SI-LIST] : Substrate modeling and analysis tool Soon Young Lee
- Re: [SI-LIST] : low-cost 2-D field solver Eric Bogatin
- RE: [SI-LIST] : low-cost 2-D field solver John Birkett
- Re: [SI-LIST] : Decoupling capacitor selection & placemen Katja Zuleeg
- [SI-LIST] : Guard banding Ronda Faries
- re: [SI-LIST] : Guard banding fabrizio zanella
- re: [SI-LIST] : Guard banding Ray Anderson
- RE: [SI-LIST] : Guard banding Elias Lozano
- re: [SI-LIST] : Guard banding [email protected]
- Re: [SI-LIST] : Substrate modeling and analysis tool Xavier Aragones
- Re: [SI-LIST] : Guard banding Ray Anderson
- [SI-LIST] : Santa Clara Valley Chapter meeting [email protected]
- Re: [SI-LIST] : Guard banding Andrew Ingraham
- [SI-LIST] : Guard banding Istvan Novak
- [SI-LIST] : Re: Guard banding Robert Voelker
- Re: [SI-LIST] : Re: Guard banding D. C. Sessions
- Re: [SI-LIST] : Re: Guard banding Jon Powell
- [SI-LIST] : New 3-D Inductance Extraction Software : CAPRI3D Yusuf Attarwala
- Re: [SI-LIST] : Re: Guard banding D. C. Sessions
- Re: [SI-LIST] : Re: Guard banding Jon Powell
- Re: [SI-LIST] : Re: Guard banding Robert Voelker
- RE: [SI-LIST] : low-cost 2-D field solver John Birkett
- [SI-LIST] : Preferred PWB impedances D. C. Sessions
- [SI-LIST] : My Resume.. Somsubhro Palchaudhury
- Re: [SI-LIST] : Preferred PWB impedances John V Fitzpatrick
- RE: [SI-LIST] : Preferred PWB impedances Greg Edlund
- Re: [SI-LIST] : Preferred PWB impedances D. C. Sessions
- Re: [SI-LIST] : Preferred PWB impedances John V Fitzpatrick
- [SI-LIST] : AGP Buffer strengths Rick Tan
- RE: [SI-LIST] : AGP Buffer strengths Elias Lozano
- Re: [SI-LIST] : Preferred PWB impedances Andrew Ingraham
- Re: [SI-LIST] : AGP Buffer strengths D. C. Sessions
- RE: [SI-LIST] : Preferred PWB impedances Mellitz, Richard
- [SI-LIST] : EMI idea or heresy Mellitz, Richard
- [SI-LIST] : EUROPEAN IBIS SUMMIT ANNOUNCEMENT Bob Ross
- [SI-LIST] : RF experience VS SI issues Weber Chuang
- [SI-LIST] : Meeting Announcement, SoCal98, Anaheim, 12May98 Bill Gaines B160 x2199
- [SI-LIST] : IBIS User Group Meeting - Dec. 4, 1997 Kathy Breda
- RE: [SI-LIST] : RF experience VS SI issues Charles Hill
- [SI-LIST] : Signal Integrity Conference in Singapore [email protected]
- [SI-LIST] : Sweeping Temp within MonteCarlo in HSPICE alaa alani
- [SI-LIST] : IBIS User Group Meeting - LOCATION/DIRECTIONS Kathy Breda
- Re: [SI-LIST] : Sweeping Temp within MonteCarlo in HSPICE Andrew Ingraham
- [SI-LIST] : DEC 4, 1997 - IBIS User Group Meeting, Additional Topic Kathy Breda
- Re: [SI-LIST] : Sweeping Temp within MonteCarlo in HSPICE Dmitri Kuznetsov
- [SI-LIST] : Other materials for GHz application [email protected]
- Re: [SI-LIST] : Other materials for GHz application [email protected]
- [SI-LIST] : Power/Ground Decoupling Methods? [email protected]
- Re: [SI-LIST] : Other materials for GHz application Paul Franzon
- [SI-LIST] : PCB Stacking! Chamseddine, Ahmad
- RE: [SI-LIST] : Other materials for GHz application Mellitz, Richard
- Re: [SI-LIST] : Other materials for GHz application Brett Grossman
- Re: [SI-LIST] : Sweeping Temp within MonteCarlo in HSPICE alaa alani
- Re: [SI-LIST] : Sweeping Temp within MonteCarlo in HSPICE alaa alani
- [SI-LIST] : Power/Ground Decoupling Methods? Larry Smith
- Re: [SI-LIST] : Power/Ground Decoupling Methods? Ray Anderson
- [SI-LIST] : EMC Issues with ASIC design Manix Velu
- Re: [SI-LIST] : EMC Issues with ASIC design Ron Matthews
- Re: [SI-LIST] : EMC Issues with ASIC design Leesa Macleod
- Re: [SI-LIST] : EMC Issues with ASIC design D. C. Sessions
- Re: [SI-LIST] : EMC Issues with ASIC design [email protected]
- [SI-LIST] : About multilayer Board Takashi Yanagimoto
- Re: [SI-LIST] : About multilayer Board Dr. Edward P. Sayre
- [SI-LIST] : Future bus backplane Garry Allen
- Re: [SI-LIST] : About multilayer Board Chee Yee Chung
- Re: [SI-LIST] : Future bus backplane L D Miller
- [SI-LIST] : HF SCSI connectors [email protected]
- [SI-LIST] : IEEE EMC meting, SF Bay Area [email protected]
- [SI-LIST] : Does solder mask reduce trace impedance ? John Lin - TAO
- RE: [SI-LIST] : Does solder mask reduce trace impedance ? John Lin - TAO
- RE: [SI-LIST] : HF SCSI connectors Charles Hill
- Re: [SI-LIST] : Does solder mask reduce trace impedance ? Kenneth Willis
- RE: [SI-LIST] : Does solder mask reduce trace impedance ? Preston Andrew MMUk
- Re: [SI-LIST] : HF SCSI connectors Don Abernathey
- RE: [SI-LIST] : Does solder mask reduce trace impedance ? Doug Brooks
- Re: [SI-LIST] : Does solder mask reduce trace impedance ? Fred Balistreri
- [SI-LIST] : TDR Measurements Mark McKee
- Re: [SI-LIST] : TDR Measurements Don Abernathey
- RE: [SI-LIST] : Does solder mask reduce trace impedance ? Ravinder Ajmani
- Re: [SI-LIST] : About multilayer Board Bob Techentin
- Re[2]: [SI-LIST] : Does solder mask reduce trace impedance ? Arpad Muranyi
- [SI-LIST] : Re: Does solder mask reduce trace impedance ? [email protected]
- [SI-LIST] : Thanks for responding my solder mask question. John Lin - TAO
- Re: [SI-LIST] : PCB Stacking! [email protected]
- [SI-LIST] : Embedded microstrip calculations, Ultracad Calculator Doug Brooks
- [SI-LIST] : Embedded microstrip calculations, Ultracad Calculator Doug Brooks
- [SI-LIST] : Virtual o-scope simulation models Roy Leventhal
- Re: [SI-LIST] : Embedded microstrip calculations, Ultracad Calculator Roy Leventhal
- Re: [SI-LIST] : Embedded microstrip calculations, Ultracad Calculator Fred Balistreri
- Re: [SI-LIST] : Embedded microstrip calculations, Ultracad Calculator Weston Beal
- [SI-LIST] : UltraCAD Calculator Doug Brooks
- [SI-LIST] : Re:HF SCSI connectors Bill Gaines B160 x2199
- [SI-LIST] : Re: Embedded microstrip calculations, Ultracad Calculator Arpad Muranyi
- [SI-LIST] : USB modeling [email protected]
- re: [SI-LIST] : Re: Embedded microstrip calculations, Ultrac... fabrizio zanella
- [SI-LIST] : Transmission Line Analysis Software Aldo Mastrosimone
- Re: [SI-LIST] : Transmission Line Analysis Software [email protected]
- Re: [SI-LIST] : Transmission Line Analysis Software Mark McKee
- Re: [SI-LIST] : Transmission Line Analysis Software Maurizio Di Zenzo
- Re: [SI-LIST] : Transmission Line Analysis Software Roland F. Portman
- [SI-LIST] : UltraCAD PCB Transmission Line Calculator Doug Brooks
- [SI-LIST] : Evaluation of Vendor tools on SI list Fred Balistreri
- [SI-LIST] : Minutes from IBIS Forum User's Meeting 12/4/97 Kathy Breda
- Re: [SI-LIST] : Evaluation of Vendor tools on SI list Roy Leventhal
- Re: [SI-LIST] : Evaluation of Vendor tools on SI list Richard A. Schumacher
- [SI-LIST] : Some questions about capacitor reliability Bob Perlman
- Re: [SI-LIST] : Evaluation of Vendor tools on SI list Don Abernathey
- Re: [SI-LIST] : Evaluation of Vendor tools on SI list Jon Powell
- Re: [SI-LIST] : USB modeling Syed Huq
- Re: [SI-LIST] : Evaluation of Vendor tools on SI list Fred Balistreri
- Re: [SI-LIST] : Some questions about capacitor reliability Fred Balistreri
- Re: [SI-LIST] : Some questions about capacitor reliability Tim Postel
- Re: [SI-LIST] : Evaluation of Vendor tools on SI list Don Abernathey
- [SI-LIST] : from SPICE to EDIF Vadim Heyfitch
- RE: [SI-LIST] : TDR Measurements Charles Hill
- RE: [SI-LIST] : TDR Measurements Mellitz, Richard
- RE: [SI-LIST] : TDR Measurements Leesa Macleod
- Re: [SI-LIST] : UltraCAD PCB Transmission Line Calculator [email protected]
- Re: [SI-LIST] : Some questions about capacitor reliability Chris Heard/US/3Com
- [SI-LIST] : RE: IBIS Open Forum minutes of 12/5 Dr. Edward P. Sayre
- Re: [SI-LIST] : TDR Measurements Mark McKee
- [SI-LIST] : Evaluation of Ventor Tools Fred Balistreri
- Re: [SI-LIST] : TDR Measurements Leesa Macleod
- Re: [SI-LIST] : Evaluation of Vendor tools on SI list Richard A. Schumacher
- [SI-LIST] : Flyback Transformer Model Lfresearch
- [SI-LIST] : TDRs and frequency domain Jay Diepenbrock
- [SI-LIST] : Call for participation: Workshop on Signal Propagation in Interconnects treytnar
- Re: [SI-LIST] : Flyback Transformer Model Michael T Zhang
- Re: [SI-LIST] : Transmission Line Analysis Software Mike Ventham
- Re: [SI-LIST] : Flyback Transformer Model Jay Diepenbrock
- [SI-LIST] : Re: IBIS connector models Dr. Edward P. Sayre
- [SI-LIST] : Re[2]: IBIS connector models [email protected]
- [SI-LIST] : "Home Made TDR" Csaba Csaszar
- [SI-LIST] : SI Engineer Gayle Standard
- [SI-LIST] : Breaking the silence: EMI/EMC "QUIET" users? John Nieznanski
- RE: [SI-LIST] : Transmission Line Analysis Software Ballard, Bowie
- [SI-LIST] : Positions Available Mackillop, William J.
- [SI-LIST] : SSO : How to identify SSO groups? Praveen G Shekokar
- Re: [SI-LIST] : SSO : How to identify SSO groups? alaa alani
- RE: [SI-LIST] : SSO : How to identify SSO groups? Greg Edlund
- [SI-LIST] : OFF TOPIC: Junk Mail and what to do with it Ray Anderson
- Re: [SI-LIST] : OFF TOPIC: Junk Mail and what to do with it Roy Leventhal
- Re: [SI-LIST] : Flyback Transformer Model Roy Leventhal
- [SI-LIST] : via/pad capacitance and resistance Roy Leventhal
- [SI-LIST] : How to identify SSO groups? Manix Velu
- Re: [SI-LIST] : How to identify SSO groups? Andrew Ingraham
- Re: [SI-LIST] : How to identify SSO groups? Joe Cahill
- [SI-LIST] : SPICE for SI analysis [email protected]
- RE: [SI-LIST] : SPICE for SI analysis John Synesiou
- RE: [SI-LIST] : SPICE for SI analysis Lin, Ted
- FW: [SI-LIST] : How to identify SSO groups? Peterson, James F
- Re: FW: [SI-LIST] : How to identify SSO groups? Scott McMorrow
- [SI-LIST] : How to identify SSO Peterson, James F
- Re: [SI-LIST] : Transmission Line Analysis Software Mike Ventham
- [SI-LIST] : Proactive SI Engineering Roger Gravrok
- [SI-LIST] : IBIS User Meeting - Jan. 15, 1998 at 3:00pm Kathy Breda
- [SI-LIST] : Output shorted to Ground! Gopala Krishna M.R.
- RE: [SI-LIST] : How to identify SSO Andrew Ingraham
- Re: [SI-LIST] : Output shorted to Ground! Fred Townsend
- Re: [SI-LIST] : How to identify SSO D. C. Sessions
- Re: [SI-LIST] : Output shorted to Ground! D. C. Sessions
- [SI-LIST] : REPOST: Breaking the silence - EMI/EMC "QUIET" users? John Nieznanski
- [SI-LIST] : SSO - How simultaneous is simultaneous? David Haedge
- Re: [SI-LIST] : How to identify SSO Jon Powell
- Re: [SI-LIST] : How to identify SSO D. C. Sessions
- Re: [SI-LIST] : How to identify SSO Jon Powell
- Re: [SI-LIST] : How to identify SSO Weber Chuang
- Re: [SI-LIST] : How to identify SSO Andrew Ingraham
- Re: [SI-LIST] : How to identify SSO Art Collard
- Re: [SI-LIST] : How to identify SSO D. C. Sessions
- [SI-LIST] : Differential Clock Routing [email protected]
- Re: [SI-LIST] : Differential Clock Routing Richard Koshak
- [SI-LIST] : EMC Society Meeting Notice, Sunnyvale, CA [email protected]
- [SI-LIST] : Software Engineering position at Mayo Medical Center Kerkhoff, Kaine A.
- Re: [SI-LIST] : How to identify SSO Weber Chuang
- [SI-LIST] : The Flight-Time/SI Effects of Trace 'Tromboning' Orr, Orville
- Re: [SI-LIST] : The Flight-Time/SI Effects of Trace 'Trombon Vadim Heyfitch
- Re: [SI-LIST] : Differential Clock Routing Hans-Joerg John
- [SI-LIST] : Signal Integrity Engineer Position Available [email protected]
- Re: [SI-LIST] : The Flight-Time/SI Effects of Trace 'Tromboning' Jon Powell
- Re: [SI-LIST] : How to identify SSO Lfresearch
- [SI-LIST] : data bus clash - how bad? Andrew Phillips
- Re: [SI-LIST] : How to identify SSO Andrew Ingraham
- Re: [SI-LIST] : data bus clash - how bad? Larry Smith
- Re: [SI-LIST] : How to identify SSO Yehuda D. Yizraeli
- [SI-LIST] : Placement of series termination Howard Johnson
- Re: [SI-LIST] : How to identify SSO Yehuda D. Yizraeli
- Re: [SI-LIST] : How to identify SSO Lfresearch
- Re: [SI-LIST] : How to identify SSO Yehuda D. Yizraeli
- Re: [SI-LIST] : The Flight-Time/SI Effects of Trace 'Tromboning' Chris Heard/US/3Com
- Re: [SI-LIST] : How to identify SSO D.C. Sessions
- Re: [SI-LIST] : How to identify SSO D.C. Sessions
- [SI-LIST] : Signal Integrity Position [email protected]
- [SI-LIST] : IEEE EMC Symposium - Denver 1998 Grasso, Charles
- [SI-LIST] : cable grounding [email protected]
- Re[2]: [SI-LIST] : How to identify SSO Arpad Muranyi
- [SI-LIST] : "Picket Fence" (Via Fence) for increasing isolation between Elya B. Joffe
- [SI-LIST] : IBIS User Group Sub-Committee Paul Galloway
- [SI-LIST] : IMAPS - OC meeting 22 jan, Micro Vias Bill Gaines B160 x2199
- [SI-LIST] : Do you have a web site for signal integrity stuff? Krull, Nick J
- Re: [SI-LIST] : Do you have a web site for signal integrity stuff? Ray Anderson
- Re: [SI-LIST] : Do you have a web site for signal integrity stuff? Paul Taddonio
- [SI-LIST] : Polylines conversion for Maxwell SI Solver YEE PAK HONG
- Re: [SI-LIST] : Polylines conversion for Maxwell SI Solver Nirmal Jain
- Re: [SI-LIST] : Polylines conversion for Maxwell SI Solver Eric Bogatin
- Re: [SI-LIST] : Do you have a web site for signal integrity Howard Johnson
- [SI-LIST] : IBIS user group meeting minutes - 1/18/98 Kathy Breda
- [SI-LIST] : Polylines conversion for Maxwell SI Solver YEE PAK HONG
- [SI-LIST] : Sensitive Info on si-list Ray Anderson
- [SI-LIST] : EMC Symposium Grasso, Charles
- [SI-LIST] : SI-LIST Eric B. Lewis
- Re: [SI-LIST] : SI-LIST Doug Brooks
- [SI-LIST] : resume - signal integrity engineer Leesa Macleod
- [SI-LIST] : CALL FOR PAPERS: 1998 IEEE Radio and Wireless Conference (RAWCON'98) (Fwd) [email protected]
- [SI-LIST] : Effective terminating voltage Kevin Weldon
- [SI-LIST] : HSPICE to QUAD models Mark Nass
- Re: [SI-LIST] : HSPICE to QUAD models Adrianus Djohan
- Re: [SI-LIST] : HSPICE to QUAD models Jon Powell
- Re: [SI-LIST] : HSPICE to QUAD models Mark Nass
- [SI-LIST] : FW: signal isolation, RF board Anthony Tse
- Re: [SI-LIST] : FW: signal isolation, RF board Fred Townsend
- NEC-LIST: test data? Juergen von Hagen
- RE: [SI-LIST] : FW: signal isolation, RF board Anthony Tse
- [SI-LIST] : EUROPEAN IBIS SUMMIT - 2nd Call Bob Ross
- [SI-LIST] : bypass cap question (long, simple) Lawrence Butcher
- Re: [SI-LIST] : bypass cap question (long, simple) Haruny Said
- RE: [SI-LIST] : bypass cap question (long, simple) Peterson, James F
- [SI-LIST] : correction : bypass cap question (long, simple) Peterson, James F
- Re: [SI-LIST] : bypass cap question (long, simple) Ronald Nikel
- Re: [SI-LIST] : bypass cap question (long, simple) Vinu Arumugham
- Re: [SI-LIST] : bypass cap question (long, simple) Philip Gantt
- Re: [SI-LIST] : bypass cap question (long, simple) Christopher Donham
- Re: [SI-LIST] : bypass cap question (long, simple) Frank Yuan
- Re: [SI-LIST] : bypass cap question (long, simple) Nirmal Jain
- [SI-LIST] : FWD: Short Courses in Applied CEM Ray Anderson
- Re: [SI-LIST] : bypass cap question (long, simple) Jeff Seeger
- Re: [SI-LIST] : bypass cap question (long, simple) Nirmal Jain
- Re: [SI-LIST] : bypass cap question (long, simple) Jeff Seeger
- Re: [SI-LIST] : bypass cap question (long, simple) Fred Balistreri
- [SI-LIST] : internal layer routing and EMI issues Weber Chuang
- RE: [SI-LIST] : internal layer routing and EMI issues Andrew Ingraham
- [SI-LIST] : Re: Differential impedance Nirmal Jain
- [SI-LIST] : Re: (Differential SCSI) D. C. Sessions
- [SI-LIST] : RE: Differential impedance John Birkett
- [SI-LIST] : Re: (Differential SCSI) Loren Koehler
- Re: [SI-LIST] : Re: Differential impedance Michael E Vrbanac
- Re: [SI-LIST] : Re: Differential impedance Weston Beal
- [SI-LIST] : Re: Differential Impedance Mike Jenkins
- [SI-LIST] : Re: Differential SCSI Fred Townsend
- [SI-LIST] : More on differential impedance calculations Mark Nass
- Re: [SI-LIST] : Re: (Differential SCSI) D. C. Sessions
- Re: [SI-LIST] : Re: (Differential SCSI) Mark Nass
- Re: [SI-LIST] : More on differential impedance calculations Fred Townsend
- Re: [SI-LIST] : Re: Differential Impedance Mike Jenkins
- [SI-LIST] : Backplanes, connectors, cables - Simulating? Wade H. Nelson
- [SI-LIST] : Differential Pairs - Different Approach Neven Pischl
- Re: [SI-LIST] : More on differential impedance calculations Wai-Yeung Yip
- Re: [SI-LIST] : Re: Differential impedance Nirmal Jain
- [SI-LIST] : Down-bond in chip packaging Yehuda D. Yizraeli
- [SI-LIST] : [MODEL CREATION] Gustavo Blando
- Re: [SI-LIST] : Down-bond in chip packaging D. C. Sessions
- Re: [SI-LIST] : Down-bond in chip packaging Yehuda D. Yizraeli
- [SI-LIST] : Differential pairs and place splits Young, Randy
- Re: [SI-LIST] : Differential pairs and place splits Vinu Arumugham
- Re: [SI-LIST] : Differential pairs and place splits Neven Pischl
- Re: [SI-LIST] : Differential pairs and place splits Neven Pischl
- [SI-LIST] : Differential Clocking & Guard Trace Michael T Zhang
- [SI-LIST] : Directions/Agenda for 2/12/98 IBIS Users' Forum Kathy Breda
- [SI-LIST] : Trace impedance measurement for dual stripline John Lin - TAO
- Re: [SI-LIST] : Differential pairs and place splits Mike Jenkins
- Re: [SI-LIST] : Differential pairs and place splits D. C. Sessions
- Re: [SI-LIST] : Down-bond in chip packaging D. C. Sessions
- Re: [SI-LIST] : Differential pairs and place splits Vinu Arumugham
- [SI-LIST] : Serpentine traces fabrizio zanella
- [SI-LIST] : [SI-LIST]: [MODEL CREATION] & IBIS models Greg Edlund
- Re: [SI-LIST] : Differential pairs and place splits Mike Jenkins
- Re: [SI-LIST] : Down-bond in chip packaging Yehuda D. Yizraeli
- RE: [SI-LIST] : Trace impedance measurement for dual stripline John Lin - TAO
- [SI-LIST] : SI openings at Stratus else delete [email protected]
- Re: [SI-LIST] : SI openings at Stratus else delete -- OBJECTIONS ... Murali Raj
- Re: [SI-LIST] : SI openings at Stratus else delete -- OBJECTIONS ... Weston Beal
- [SI-LIST] : Job Postings on si-list Ray Anderson
- Re: [SI-LIST] : SI openings at Stratus else delete -- OBJECTIONS ... Al Barber
- Re: [SI-LIST] : SI openings at Stratus else delete -- OBJECTIONS ... Prasad Modali - Katmai Design
- Re: [SI-LIST] : SI openings at Stratus else delete -- OBJECT Joe Cahill
- Re: [SI-LIST] : SI openings at Stratus -- ... last one Murali Raj
- Re: [SI-LIST] : SI openings at Stratus -- ... last one Frank Yuan
- [SI-LIST] : Intelligent Placement of Decoupling Capacitors Raymond Chen
- Re: [SI-LIST] : SI openings at Stratus -- ... last one Kazi Hassan
- [SI-LIST] : model translation Bob Meyer
- [SI-LIST] : Modeling Package parasitics Mark Nass
- Re: [SI-LIST] : Modeling Package parasitics D. C. Sessions
- Re: [SI-LIST] : Modeling Package parasitics Chee Yee Chung
- Re: [SI-LIST] : Modeling Package parasitics Gregory P. Fitzgerald
- Re: [SI-LIST] : Modeling Package parasitics Mike Jenkins
- Re: [SI-LIST] : Modeling Package parasitics D. C. Sessions
- [SI-LIST] : Earth Ground Melinda Piket-May
- Re: [SI-LIST] : Earth Ground Fred Townsend
- Re : [SI-LIST] : Modeling Package parasitics Weber Chuang
- Re: [SI-LIST] : Earth Ground Doug Brooks
- Re: [SI-LIST] : Modeling Package parasitics Anders Ekholm
- Re[2]: [SI-LIST] : Modeling Package parasitics Chee Yee Chung
- Re: [SI-LIST] : Earth Ground Jerry Johnson
- Re: [SI-LIST] : SI openings at Stratus else delete -- OBJECTIONS ... Gary Fowler
- Re: [SI-LIST] : Modeling Package parasitics Mattan Kamon
- Re: [SI-LIST] : Earth Ground [email protected]
- [[email protected]: Re: [SI-LIST] : Earth Ground] Mark McKee
- RE: [SI-LIST] : Earth Ground Andrew Ingraham
- Re: [[email protected]: Re: [SI-LIST] : Earth Ground] Fred Townsend
- Re: [SI-LIST] : SI openings at Stratus else delete -- OBJECTIONS ... Alan Heinbaugh
- [SI-LIST] : PCB design techniques for EMC control Lund, Steve
- Re: [SI-LIST] : SI-LIST Howard Johnson
- Re: [SI-LIST] : Serpentine traces Howard Johnson
- Re: [SI-LIST] : Earth Ground Howard Johnson
- Re: [SI-LIST] : Earth Ground Howard Johnson
- Re: [SI-LIST] : Modeling Package parasitics Howard Johnson
- [SI-LIST] : Interesting si-list statistics Ray Anderson
- Re: [SI-LIST] : Modeling Package parasitics D. C. Sessions
- [SI-LIST] : Oscillator or Crystal Mike Mayer
- Re: [SI-LIST] : PCB design techniques for EMC control Ron Matthews
- Re: [SI-LIST] : PCB design techniques for EMC control Roland F. Portman
- Fwd: [SI-LIST] : PCB design techniques for EMC control [email protected]
- [SI-LIST] : AGENDA EUROPEAN IBIS SUMMIT 2/26/98 Bob Ross
- [SI-LIST] : PC Choice [email protected]
- [SI-LIST] : To overshoot or undershoot: ( to diode or not to diode) Mellitz, Richard
- [SI-LIST] : IBIS User Forum Meeting Minutes - 2/12/98 Kathy Breda
- [SI-LIST] : Differential SCSI BP design John Lin - TAO
- RE: [SI-LIST] : To overshoot or undershoot: ( to diode or not to Andrew Ingraham
- RE: [SI-LIST] : To overshoot or undershoot: ( to diode or not to diode) Mellitz, Richard
- [SI-LIST] : Overshoot/Undershoot Bill Dempsey
- RE: [SI-LIST] : To overshoot or undershoot: ( to diode or not to Andrew Ingraham
- Re: [SI-LIST] : Overshoot/Undershoot D. C. Sessions
- Re: [SI-LIST] : Overshoot/Undershoot Bill Dempsey
- Re: [SI-LIST] : Overshoot/Undershoot Mike Mayer
- Re: [SI-LIST] : Overshoot/Undershoot Arpad Muranyi
- Re: [SI-LIST] : Overshoot/Undershoot D. C. Sessions
- Re: [SI-LIST] : Overshoot/Undershoot Steve Williams
- RE: [SI-LIST] : Overshoot/Undershoot Barnes, Larry
- RE: [SI-LIST] : Overshoot/Undershoot Grebenkemper, John
- RE: [SI-LIST] : Overshoot/Undershoot Grebenkemper, John
- [SI-LIST] : Crystal Oscillator Vs Resonator Ravinder Ajmani
- RE: [SI-LIST] : Overshoot/Undershoot: Mellitz, Richard
- RE: [SI-LIST] : Overshoot/Undershoot Andrew Ingraham
- Re: [SI-LIST] : Crystal Oscillator Vs Resonator [email protected]
- Re: [SI-LIST] : Overshoot/Undershoot: D. C. Sessions
- Re: [SI-LIST] : Overshoot/Undershoot D. C. Sessions
- [SI-LIST] : Re: [SI-LIST] - Overshoot/U MARK GAILUS
- [SI-LIST] : Crystal Oscillator Vs Resonator [email protected]
- RE: [SI-LIST] : Overshoot/Undershoot: Mellitz, Richard
- [SI-LIST] : Diff measurements with VNA Katie Rothstein
- re: [SI-LIST] : Diff measurements with VNA fabrizio zanella
- Re: [SI-LIST] : Diff measurements with VNA John V Fitzpatrick
- Re: [SI-LIST] : Diff measurements with VNA Roy Leventhal
- [SI-LIST] : CMOS off-chip driver design Michael Gutzmann
- [SI-LIST] : Re: CMOS off-chip driver design Michael Gutzmann
- Re: [SI-LIST] : CMOS off-chip driver design Yehuda D. Yizraeli
- Re: [SI-LIST] : Diff measurements with VNA Ryszard Vogel
- [SI-LIST] : Hyperlynx IBIS Developer Tool Kit - Action Item from IBIS User Kathy Breda
- [SI-LIST] : Types of Bypass Caps Pavlak, John M
- Re: [SI-LIST] : Types of Bypass Caps Fred Townsend
- [SI-LIST] : 4 March 98 Meeting, Tech Soci NepconWest (Anaheim, Calif) Bill Gaines B160 x2199
- [SI-LIST] : Driver Strength Mark Nass
- Re: [SI-LIST] : Driver Strength Yehuda D. Yizraeli
- [SI-LIST] : Signal Integrity position open at 3Com Mohammad Ali
- RE: [SI-LIST] : Driver Strength Greg Edlund
- [SI-LIST] : transmission line theory Bodley, Andrew
- Re: [SI-LIST] : transmission line theory Stephen Peters
- RE: [SI-LIST] : transmission line theory Greg Edlund
- RE: [SI-LIST] : Driver Strength Kazi Hassan
- Re: [SI-LIST] : SMA Impedance Matching [email protected]
- [SI-LIST] : SMA Impedance Matching [email protected]
- Re: [SI-LIST] : SMA Impedance Matching Michael A. Baxter
- Re: [SI-LIST] : SMA Impedance Matching [email protected]
- [SI-LIST] : SMA Impedance Matching Jay Diepenbrock
- [SI-LIST] : SMA Impedance Matching Jay Diepenbrock
- [SI-LIST] : Looking for Signal Integrity Engineers Steven Ray
- Re: [SI-LIST] : Driver Strength D. C. Sessions
- Re: [SI-LIST] : Driver Strength Lfresearch
- Re: [SI-LIST] : Driver Strength Mark Nass
- [SI-LIST] : power supply filtering and bypassing Skey, Kevin
- Re: [SI-LIST] : Driver Strength D. C. Sessions
- Re: [SI-LIST] : Driver Strength D. C. Sessions
- Re: [SI-LIST] : power supply filtering and bypassing Philip R. Gantt
- Re: [SI-LIST] : power supply filtering and bypassing Michael T Zhang
- Re: [SI-LIST] : power supply filtering and bypassing Ravinder Ajmani
- Re: [SI-LIST] : power supply filtering and bypassing [email protected]
- [SI-LIST] : Question about Gear vs Trapezoidal methods for simulations within HSPICe Elias Lozano
- [SI-LIST] : End launch SMA connectors Jay Diepenbrock
- Re: [SI-LIST] : Driver Strength Lfresearch
- Re: [SI-LIST] : power supply filtering and bypassing Roy Leventhal
- Re: [SI-LIST] : power supply filtering and bypassing Paul Thompson
- Re: [SI-LIST] : Question about Gear vs Trapezoidal methods for simulations within HSPICe Dmitri Kuznetsov
- Re: [SI-LIST] : Question about Gear vs Trapezoidal methods for simulations within HSPICe J. Eric Bracken
- Re: [SI-LIST] : power supply filtering and bypassing John Fisher
- Re[2]: [SI-LIST] : power supply filtering and bypassing [email protected]
- Re[2]: [SI-LIST] : power supply filtering and bypassing Ray Anderson
- RE: Re[2]: [SI-LIST] : power supply filtering and bypassing Skey, Kevin
- [SI-LIST] : IBIS Accuracy Sub-Committee Minutes Greg Edlund
- Re: Re[2]: [SI-LIST] : power supply filtering and bypassing John Fisher
- Re: Re[2]: [SI-LIST] : power supply filtering and bypassing Jeff M. Gloudemans
- Re: Re[2]: [SI-LIST] : power supply filtering and bypassing Ray Anderson
- Re: [SI-LIST] : power supply filtering and bypassing Richard Wheeler
- Re: Re[2]: [SI-LIST] : power supply filtering and bypassing Istvan NOVAK
- [SI-LIST] : si-list archives restored Ray Anderson
- Re: [SI-LIST] : Driver Strength chong lin
- Re: [SI-LIST] : power supply filtering and bypassing Michael Tsuk
- [SI-LIST] : IBIS User Group Meeting Reminder - Thurs., 3/19/98, 3:00 PM Kathy Breda
- [SI-LIST] : Electrical Package Characterization Engineer Nozad Karim
- [SI-LIST] : Ansoft HFSS Technical Workshop, May 14, 15 Eric Bogatin
- [SI-LIST] : =?ISO-8859-1?Q?[SI-LIST]:_2nd_IEEE_Workshop_=22Signal_Propagation_on_Interconnects=22?= Treytnar Dieter
- [SI-LIST] : job opening Yoon Kim
- [SI-LIST] : Proposal for an IBIS Accuracy Specification Kathy Breda
- [SI-LIST] : IBIS USER Meeting - 3/19/98, 3:00PM, at DEC, Hudson, MA Kathy Breda
- [SI-LIST] : PCB Pwr Planes Peterson, James F
- Re: [SI-LIST] : PCB Pwr Planes Samie Samaan
- Re: [SI-LIST] : PCB Pwr Planes [email protected]
- Re: [SI-LIST] : PCB Pwr Planes Hemant Shah
- Re: [SI-LIST] : PCB Pwr Planes Mark Randol
- Re: [SI-LIST] : PCB Pwr Planes [email protected]
- RE: [SI-LIST] : PCB Pwr Planes John Lin - TAO
- [SI-LIST] : newbye Fabrice ILPONSE
- [SI-LIST] : Effective Dielectric [email protected]
- Re: [SI-LIST] : Effective Dielectric D. C. Sessions
- [SI-LIST] : Controlled impedance in Flex Circuit Roland F. Portman
- [SI-LIST] : Signal Integrity/Board design Elias Lozano
- Re: [SI-LIST] : Effective Dielectric Weber Chuang
- [SI-LIST] : Cable skew Muzahid Huda
- re: [SI-LIST] : Controlled impedance in Flex Circuit fabrizio zanella
- [SI-LIST] : re: cable skew Del Cecchi
- [SI-LIST] : Re: Controlled impedance in Flex Circuit Heyfitch, Vadim
- [SI-LIST] : IBIS Modeling [email protected]
- Re: [SI-LIST] : IBIS Modeling D. C. Sessions
- [SI-LIST] : High Speed Design Symposium greg doyle
- Re: [SI-LIST] : newbye Francesc Moll
- [SI-LIST] : Re: Cable Skew [email protected]
- Re: [SI-LIST] : IBIS Modeling Ray Anderson
- RE: [SI-LIST] : Effective Dielectric Andrew Ingraham
- RE: [SI-LIST] : Cable skew Andrew Ingraham
- [SI-LIST] : =?ISO-8859-1?Q?[SI-LIST]:_Premiere_course_on_=22Circuit_Simulation_and_Signal_Integrity= Hartmut Grabinski
- Re: [SI-LIST] : IBIS Modeling Kellee Crisafulli
- RE : [SI-LIST] : IBIS Modeling Weber Chuang
- RE: [SI-LIST] : IBIS Modeling Andrew Ingraham
- RE: [SI-LIST] : IBIS Modeling Kellee Crisafulli
- Re: [SI-LIST] : EMI Measurement [email protected]
- RE: [SI-LIST] : Cable skew Charles Hill
- Re: [SI-LIST] : Controlled impedance in Flex Circuit Shawn Carpenter
- [SI-LIST] : Impedance of micro-strip over wide ground trace Roland F. Portman
- Re: [SI-LIST] : Controlled impedance in Flex Circuit Shawn Carpenter
- [SI-LIST] : ?Dumb Question Regarding Multilayer Boards Mark Randol
- Re: [SI-LIST] : Impedance of micro-strip over wide ground trace [email protected]
- [SI-LIST] : Power Supply Noise Filters Khalid Ansari
- RE: [SI-LIST] : SPICE or IBIS SI models Bishop, Ron
- Re: [SI-LIST] : SPICE or IBIS SI models Syed Huq
- Re: [SI-LIST] : ?Dumb Question Regarding Multilayer Boards Mark Randol
- [SI-LIST] : SPICE or IBIS SI models csoolan
- [SI-LIST] : Parasitics + timing (any idea) Fabrice ILPONSE
- Re: [SI-LIST] : ?Dumb Question Regarding Multilayer Boards Jeff Seeger
- Re: [SI-LIST] : Controlled impedance in Flex Circuit [email protected]
- Re: [SI-LIST] : Power Supply Noise Filters Michael T Zhang
- Re: [SI-LIST] : Controlled impedance in Flex Circuit Shawn Carpenter
- Re: [SI-LIST] : Controlled impedance in Flex Circuit [email protected]
- RE: [SI-LIST] : Modeling Package parasitics Charles Hill
- Re[2]: [SI-LIST] : Controlled impedance in Flex Circuit Chee Yee Chung
- Re[2]: [SI-LIST] : Controlled impedance in Flex Circuit Chee Yee Chung
- Re: [SI-LIST] : Controlled impedance in Flex Circuit Vinu Arumugham
- [SI-LIST] : NOTE 03/30/98 16:24:58 [email protected]
- Re: [SI-LIST] : Power Supply Noise Filters Khalid Ansari
- Re[2]: [SI-LIST] : Power Supply Noise Filters Michael T Zhang
- [SI-LIST] : RE: MODEL CREATION Roy Leventhal
- Re[2]: [SI-LIST] : Power Supply Noise Filters [email protected]
- Re: [SI-LIST] : RE: MODEL CREATION Roy Leventhal
- [SI-LIST] : SPICE Buffer Models Elizabeth Perigault
- Re: [SI-LIST] : SPICE Buffer Models Ray Anderson
- Re: [SI-LIST] : SPICE Buffer Models Elizabeth Perigault
- [SI-LIST] : ibis,si-list,looking for ibis models Wang Lin
- Re: [SI-LIST] : SPICE Buffer Models Savithri S.
- [SI-LIST] : IBIS AND EMC [email protected]
- [Fwd: [SI-LIST] : IBIS AND EMC] Michael Wehmeier
- [SI-LIST] : Output Impedance alaa alani
- Re: [SI-LIST] : Output Impedance D. C. Sessions
- Re: [SI-LIST] : Output Impedance Kevin Weldon
- FW: [SI-LIST] : Output Impedance George Harris
- Re: [SI-LIST] : IBIS AND EMC Christian Nause
- Re: [SI-LIST] : Output Impedance Larry Smith
- FW: [SI-LIST] : Output Impedance Zenklusen, Fred
- RE: Re: [SI-LIST] : IBIS AND EMC [email protected]
- [SI-LIST] : Differential Reflection Question Lehew, John
- Re: [SI-LIST] : SPICE Buffer Models Mark Randol
- Re: [SI-LIST] : SPICE Buffer Models Savithri S.
- [SI-LIST] : Convert an IBIS model to SPICE Model. John Lin - TAO
- RE: [SI-LIST] : Output Impedance Andrew Ingraham
- Re: [SI-LIST] : Convert an IBIS model to SPICE Model. D. C. Sessions
- Re: [SI-LIST] : Output Impedance Brian Young
- Re: [SI-LIST] : Output Impedance D. C. Sessions
- RE: [SI-LIST] : Output Impedance Greg Edlund
- Re: [SI-LIST] : Output Impedance Larry Smith
- RE: [SI-LIST] : Convert an IBIS model to SPICE Model. John Synesiou
- Re: [SI-LIST] : Differential Reflection Question Alok Tripathi
- Re: FW: [SI-LIST] : Output Impedance Arpad Muranyi
- Re: [SI-LIST] : Convert an IBIS model to SPICE Model. D. C. Sessions
- [SI-LIST] : RE:Termination of High Speed Bus Brent Joyce
- Re[2]: [SI-LIST] : Output Impedance Arpad Muranyi
- Re: FW: [SI-LIST] : Output Impedance [email protected]
- [SI-LIST] : Self-inductance [email protected]
- RE: [SI-LIST] : Convert an IBIS model to SPICE Model. Andrew Ingraham
- Re: [SI-LIST] : Self-inductance D. C. Sessions
- Re: [SI-LIST] : Self-inductance D. C. Sessions
- RE: [SI-LIST] : Convert an IBIS model to SPICE Model. John Synesiou
- [SI-LIST] : curve tracers and Output Impedance Sandy Taylor
- [SI-LIST] : Freq. dependent losses in Spice? Brett Grossman
- Re: [SI-LIST] : RE:Termination of High Speed Bus Doug Brooks
- Re: [SI-LIST] : curve tracers and Output Impedance D. C. Sessions
- RE: [SI-LIST] : curve tracers and Output Impedance Andrew Ingraham
- [SI-LIST] : FIXED: curve tracers and Output Impedance Sandy Taylor
- Re: [SI-LIST] : Convert an IBIS model to SPICE Model. Fred Balistreri
- RE: [SI-LIST] : Convert an IBIS model to SPICE Model. John Synesiou
- [SI-LIST] : Lowering ASIC noise Lfresearch
- Re[2]: [SI-LIST] : Convert an IBIS model to SPICE Model. Arpad Muranyi
- FW: [SI-LIST] : FIXED: curve tracers and Output Impedance Heyfitch, Vadim
- [SI-LIST] : ASIC noise update.... Lfresearch
- Re: FW: [SI-LIST] : FIXED: curve tracers and Output Impedance Sandy Taylor
- Re: [SI-LIST] : ASIC noise update.... D. C. Sessions
- [SI-LIST] : OPENING: Signal Integrity Engineer, Juniper Networks Heinz Blennemann
- [SI-LIST] : Precision Clocking GEisler
- Re: [SI-LIST] : Precision Clocking D. C. Sessions
- Re: [SI-LIST] : Output Impedance D. C. Sessions
- Re: [SI-LIST] : Precision Clocking HaroldLSJ
- [SI-LIST] : Crystal Question Goodarz Goodarzi
- Re: [SI-LIST] : Precision Clocking GEisler
- Re: [SI-LIST] : Crystal Question Ray Anderson
- Re:[SI-LIST] : Crystal Question [email protected]
- [SI-LIST] : IBIS User Group minutes 3/19 - In future will only be sent to Kathy Breda
- [SI-LIST] : PCI Slew Rate Test Load Chan, Michael
- RE: [SI-LIST] : PCI Slew Rate Test Load Andrew Ingraham
- RE: [SI-LIST] : PCI Slew Rate Test Load Farrokh Mottahedin
- [SI-LIST] : How to do correlation with two extra Rising/Falling waveforms? John Lin - TAO
- [SI-LIST] : Spice models Mackillop, William J.
- [SI-LIST] : viewing HSPICE results without awaves Mike Degerstrom
- Re: [SI-LIST] : viewing HSPICE results without awaves Ray Anderson
- RE: [SI-LIST] : viewing HSPICE results without awaves Andrew Ingraham
- RE: [SI-LIST] : viewing HSPICE results without awaves Andrew Ingraham
- [SI-LIST] : Alternative viewer for Hspice .ac0,.tr0,.sw0 files Ray Anderson
- Re: [SI-LIST] : viewing HSPICE results without awaves Joe Cahill
- [SI-LIST] : measuring CMOS Cin with HP4275A Greg Edlund
- Re: [SI-LIST] : measuring CMOS Cin with HP4275A Mike Degerstrom
- RE: [SI-LIST] : measuring CMOS Cin with HP4275A Andrew Ingraham
- [SI-LIST] : Re: How to do correlation with two extra Rising/Falling waveforms? Stephen Peters
- RE: [SI-LIST] : measuring CMOS Cin with HP4275A Shenoy, Jay
- RE: [SI-LIST] : measuring CMOS Cin with HP4275A Charles Hill
- [SI-LIST] : Decoupling Capacitors Raman Muthukrishnan
- Re: [SI-LIST] : Decoupling Capacitors Mark Randol
- Re: [SI-LIST] : Decoupling Capacitors Raman Muthukrishnan
- [SI-LIST] : 66 MHz AGP Clock Signal Diaco Davari
- [SI-LIST] : Looking for corner PCI spice models McCormick, Robert
- [SI-LIST] : Re: measuring CMOS Cin with HP4275A Mike Jenkins
- Re: [SI-LIST] : Re: measuring CMOS Cin with HP4275A - IPA510 Syed Huq
- Re: [SI-LIST] : 66 MHz AGP Clock Signal [email protected]
- [SI-LIST] : stackup question Paul Thompson
- RE: [SI-LIST] : 66 MHz AGP Clock Signal Chamseddine, Ahmad
- Re: [SI-LIST] : stackup question D. C. Sessions
- Re: [SI-LIST] : stackup question Ravinder Ajmani
- [SI-LIST] : QUAD Model & Device capacitance Mark Nass
- [SI-LIST] : stackup question Roland F. Portman
- Re: [SI-LIST] : stackup question John Fisher
- RE: [SI-LIST] : stackup question Peterson, James F
- RE: [SI-LIST] : stackup question Silbert, Steven F.
- RE: [SI-LIST] : 66 MHz AGP Clock Signal Andrew Ingraham
- [SI-LIST] : Determining CMOS Cin with TDR methodology Dr. Edward P. Sayre
- [SI-LIST] : Dual Stripline impedance Magnus Homann
- [SI-LIST] : Re: Determining CMOS Cin with TDR methodology [email protected]
- RE: [SI-LIST] : Dual Stripline impedance Silbert, Steven F.
- Re: [SI-LIST] : Dual Stripline impedance Ravinder Ajmani
- Re: [SI-LIST] : Dual Stripline impedance Mike Degerstrom
- [SI-LIST] : Synchronous SRAM Application Jim McNamara
- RE: [SI-LIST] : Dual Stripline impedance Michael A. Baxter
- [SI-LIST] : Re: QUAD Model & Device capacitance Jon Dowling
- Re: [SI-LIST] : Dual Stripline impedance Vinu Arumugham
- Re: [SI-LIST] : Dual Stripline impedance [email protected]
- [SI-LIST] : Disconnect Requests Sent to si-list Ray Anderson
- RE: [SI-LIST] : 66 MHz AGP Clock Signal Diaco Davari
- Re: [SI-LIST] : Dual Stripline impedance Fred Balistreri
- [SI-LIST] : tying clock outputs to reduce skew? [email protected]
- [SI-LIST] : Re: Dual Stripline impedance Juliusz Poltz
- Re: [SI-LIST] : tying clock outputs to reduce skew? Vinu Arumugham
- [SI-LIST] : uBGA high frequency characteristics Scott McMorrow
- [SI-LIST] : Looking for Signal Integrity Engineers Rambus Inc.
- [SI-LIST] : How to measure MOS capacitance Yehuda D. Yizraeli
- [SI-LIST] : Need your comments in selection of SI simulation tool! [email protected]
- [SI-LIST] : Opportunity at Dell Hart, Frances
- Re: [SI-LIST] : How to measure MOS capacitance D. C. Sessions
- Re: [SI-LIST] : Need your comments in selection of SI simula Michael Cohen
- RE: [SI-LIST] : How to measure MOS capacitance Muranyi, Arpad
- [SI-LIST] : VMEbus transceivers O'Donnell, John
- RE: [SI-LIST] : How to measure MOS capacitance Andrew Ingraham
- [SI-LIST] : Looking for SI consultants in the North East Paul Franzon
- Re: [SI-LIST] : Dual Stripline impedance Magnus Homann
- AW: [SI-LIST] : How to measure MOS capacitance Unger Bernhard
- Re: [SI-LIST] : VMEbus transceivers Ramzi Ammar
- [SI-LIST] : passive cable equalization network Christopher Albert
- Re: [SI-LIST] : Dual Stripline impedance [email protected]
- Re: [SI-LIST] : VMEbus transceivers Ramzi Ammar
- [SI-LIST] : Ground bounce caused by VMEbus transceivers O'Donnell, John
- RE : [SI-LIST] : Need your comments in selection of SI simula Weber Chuang
- [SI-LIST] : Switching current and pull-down current Weber Chuang
- RE: [SI-LIST] : How to measure MOS capacitance Yehuda D. Yizraeli
- [SI-LIST] : Worst case VI curve for PCI spec a reality? McCormick, Robert
- Re: [SI-LIST] : Worst case VI curve for PCI spec a reality? Yehuda D. Yizraeli
- RE : [SI-LIST] : Need your comments in selection of SI simula Bishop, Ron
- RE: [SI-LIST] : Worst case VI curve for PCI spec a reality? Andrew Ingraham
- Re: [SI-LIST] : Worst case VI curve for PCI spec a reality? Scott McMorrow
- Re: [SI-LIST] : Worst case VI curve for PCI spec a reality? D. C. Sessions
- Re: [SI-LIST] : Worst case VI curve for PCI spec a reality? Scott McMorrow
- Re: [SI-LIST] : Worst case VI curve for PCI spec a reality? D. C. Sessions
- RE : [SI-LIST] : Need your comments in selection of SI simula Rick Jones
- Re: [SI-LIST] : Worst case VI curve for PCI spec a reality? Scott McMorrow
- [SI-LIST] : update on measuring CMOS Cin with HP4275A Greg Edlund
- [SI-LIST] : Inductance vs. frequency Lidu Huang
- Re: [SI-LIST] : Inductance vs. frequency Wai-Yeung Yip
- Re: [SI-LIST] : Inductance vs. frequency Raghu
- [SI-LIST] : Cross section geometry for the previous post on inductance Lidu Huang
- RE: [SI-LIST] : Worst case VI curve for PCI spec a reality? Andrew Ingraham
- Re: [SI-LIST] : Worst case VI curve for PCI spec a reality? D. C. Sessions
- [SI-LIST] : Final report on inductance vs. frequency Lidu Huang
- [SI-LIST] : Output Driver Impedance Variation? Bob Perlman
- RE: [SI-LIST] : Cross section geometry for the previous post Chung, Chee Yee
- [SI-LIST] : IEEE (where to find them freely on the web?) Fabrice ILPONSE
- RE: [SI-LIST] : Output Driver Impedance Variation? Andrew Ingraham
- RE: [SI-LIST] : Inductance vs. frequency [email protected]
- Re: [SI-LIST] : Serpentine traces Paul Thompson
- Re: [SI-LIST] : Serpentine traces D. C. Sessions
- Re: [SI-LIST] : stackup question D. C. Sessions
- [SI-LIST] : Ansoft 2D extractor question Grasso, Charles
- [SI-LIST] : Ferrite Beads in HSPICE Julia Nekrylova
- [SI-LIST] : Unconnected headers and connectors Scott Bronson
- [SI-LIST] : attenuation calculations Craig Callen
- Re: [SI-LIST] : Ferrite Beads in HSPICE Dmitri Kuznetsov
- RE: [SI-LIST] : Ansoft 2D extractor question Chung, Chee Yee
- [SI-LIST] : Re: attenuation calculations Juliusz Poltz
- R: [SI-LIST] : Serpentine traces [email protected]
- Re: [SI-LIST] : Ansoft 2D extractor question [email protected]
- Re: [SI-LIST] : Ansoft 2D extractor question J. Eric Bracken
- Re: [SI-LIST] : Ansoft 2D extractor question Eric Bogatin
- [SI-LIST] : Re: attenuation calculations Craig Callen
- Re: [SI-LIST] : Inductance vs. frequency [email protected]
- Re: [SI-LIST] : Inductance vs. frequency [email protected]
- [SI-LIST] : Incorporating 3-d passive circuit models into SPICE Mike Degerstrom
- [SI-LIST] : Re: attenuation calculations Juliusz Poltz
- Re: [SI-LIST] : Incorporating 3-d passive circuit models into SPICE Ray Anderson
- Re: [SI-LIST] : Incorporating 3-d passive circuit models into SPICE Fred Balistreri
- Re: [SI-LIST] : Inductance vs. frequency Fred Balistreri
- Re: [SI-LIST] : Incorporating 3-d passive circuit models into Dr. Edward P. Sayre
- [SI-LIST] : Extraction of mutual inductance and mutual capacitance from VNA Yee Pak Hong
- [SI-LIST] : Decoupling:routing DFONTANE
- Re: [SI-LIST] : Decoupling:routing Ravinder Ajmani
- Re: [SI-LIST] : Decoupling:routing Doug Brooks
- Re: [SI-LIST] : Decoupling:routing Scott Bronson
- [SI-LIST] : Modeling BGAs with floating ground plane Mike Degerstrom
- Re: [SI-LIST] : Modeling BGAs with floating ground plane Raghu
- Re: [SI-LIST] : Decoupling:routing Tom Zimmerman
- [SI-LIST] : another stack-up question Andrew Phillips
- [SI-LIST] : Switching current and pull-down current Weber Chuang
- Re: [SI-LIST] : Incorporating 3-d passive circuit models into SPICE Salvador Iranzo
- Re: [SI-LIST] : Output Driver Impedance Variation? Art Collard
- Re: [SI-LIST] : Decoupling:routing Tom Zimmerman
- [SI-LIST] : Does SSO make outputs earlier as well as later? Andrew Ingraham
- Re: [SI-LIST] : Does SSO make outputs earlier as well as later? Jon Powell
- Re: [SI-LIST] : Does SSO make outputs earlier as well as later? YES, BUT... Chip Chip
- Re: [SI-LIST] : Decoupling:routing larry smith
- Re: [SI-LIST] : another stack-up question D. C. Sessions
- [SI-LIST] : Self and mutual inductance Lidu Huang
- Re: [SI-LIST] : another stack-up question Paul Taddonio
- Re: [SI-LIST] : Self and mutual inductance Lidu Huang
- Re: [SI-LIST] : another stack-up question D. C. Sessions
- [SI-LIST] : Fwd: EMI/SI Job Opening @Ridge Technologies Pam Headsten
- Re: [SI-LIST] : another stack-up question Vinu Arumugham
- [SI-LIST] : Screened/Shielded UTP Cabling craig stein
- [SI-LIST] : A 10 layer stackup Peterson, James F
- [SI-LIST] : Lossy lines,TDR and connectors Chris Knapton
- [SI-LIST] : Re: SI-LIST - Self and mutual inductance Juliusz Poltz
- Re: [SI-LIST] : Decoupling:routing Jay Diepenbrock
- [SI-LIST] : Guard Trace Effect on Impedence Robert K Huber
- [SI-LIST] : Propagation velocity / discontinuous reference plane Preston Andrew MMUk
- [SI-LIST] : bga Tom Giovannini
- RE: [SI-LIST] : bga Perez, Raul
- Re: [SI-LIST] : Propagation velocity / discontinuous reference plane larry smith
- Re: [SI-LIST] : bga Roland F. Portman
- [SI-LIST] : Re: Propagation velocity / discontinuous reference plane Mike Jenkins
- Re: [SI-LIST] : Propagation velocity / discontinuous reference plane Weston Beal
- Re: [SI-LIST] : bga Gregory P. Fitzgerald
- Re: [SI-LIST] : Propagation velocity / discontinuous reference plane Xiaojun Zhu
- Re: [SI-LIST] : Propagation velocity / discontinuous referen [email protected]
- [SI-LIST] : Request to SI list Administrator [email protected]
- [SI-LIST] : Signal Integrity Positions Mark Gregory
- [SI-LIST] : Clock Verification Seminar Tina Engel
- Re: [SI-LIST] : Guard Trace Effect on Impedence Michael Freda
- Re: [SI-LIST] : Propagation velocity / discontinuous reference plane Xiaojun Zhu
- Re: [SI-LIST] : bga Jeff Seeger
- RE: [SI-LIST] : Propagation velocity / discontinuous reference pl Andrew Ingraham
- Re: [SI-LIST] : Propagation velocity / discontinuous reference [email protected]
- Re: [SI-LIST] : Propagation velocity / discontinuous reference pl ane Chris Cheng
- [SI-LIST] : field solver for differential pairs Silbert, Steven F.
- RE: [SI-LIST] : field solver for differential pairs Walker, Jim
- Re: [SI-LIST] : bga Roland F. Portman
- [SI-LIST] : Power Plane Thickness Mike Mayer
- [SI-LIST] : Clock and Transmission Line Termination Eric B. Lewis
- RE: [SI-LIST] : Decoupling:routing Grasso, Charles
- [SI-LIST] : Diodes, EMC, ESD Protection networks Peter Baxter
- Re: [SI-LIST] : Diodes, EMC, ESD Protection networks Magnus Homann
- Re: [SI-LIST] : Diodes, EMC, ESD Protection networks [email protected]
- Re: [SI-LIST] : Diodes, EMC, ESD Protection networks Gary Crowell Sr.
- Re: [SI-LIST] : Clock and Transmission Line Termination Dennis Tomlinson
- RE: [SI-LIST] : Diodes, EMC, ESD Protection networks Charles Hill
- [SI-LIST] : Re: PCB Top Gun Showdown! Ronda Faries
- [SI-LIST] : eye patterns Craig Callen
- Re: [SI-LIST] : eye patterns Brett Grossman
- Re: [SI-LIST] : eye patterns Mike Degerstrom
- Re: [SI-LIST] : eye patterns Randy Hamilton
- [SI-LIST] : IBIS to Spice Philip R. Gantt
- [SI-LIST] : Re: eye patterns Mike Jenkins
- Re: [SI-LIST] : IBIS to Spice Syed Huq
- Re: [SI-LIST] : IBIS to Spice D. C. Sessions
- Re: [SI-LIST] : IBIS to Spice Philip R. Gantt
- Re: [SI-LIST] : IBIS to Spice Fred Balistreri
- [SI-LIST] : Does IBIS describe output transition which both MOS turned on? John Lin - TAO
- Re: [SI-LIST] : Does IBIS describe output transition which both MOS turned on? Vinu Arumugham
- fwd: Re: [SI-LIST] : Does IBIS describe output transition which both Jean-Claude Perrin
- Re: fwd: Re: [SI-LIST] : Does IBIS describe output transition which both A. D. Shirpadaraj
- Re: [SI-LIST] : Does IBIS describe output transition which both D. C. Sessions
- Re: [SI-LIST] : Does IBIS describe output transition which both MOS turned on? Fred Balistreri
- [SI-LIST] : Excessive clock overshoot fabrizio zanella
- Re: [SI-LIST] : Excessive clock overshoot D. C. Sessions
- Re: [SI-LIST] : Does IBIS describe output transition which both MOS turned on? D. C. Sessions
- RE: [SI-LIST] : Excessive clock overshoot Andrew Ingraham
- Re: [SI-LIST] : Does IBIS describe output transition which both MOS turned on? D. C. Sessions
- Re: [SI-LIST] : Does IBIS describe output transition which both MOS turned on? Fred Balistreri
- [SI-LIST] : ANY EXPERIENCE OF MENTOR'S IS TOOLS John Heighton
- Re: [SI-LIST] : Does IBIS describe output transition which both MOS turned on? Chris Rokusek
- RE: [SI-LIST] : Excessive clock overshoot Charles Hill
- [SI-LIST] : Is feedback really EVIL? Charles Hill
- Re: [SI-LIST] : Excessive clock overshoot fabrizio zanella
- Re: [SI-LIST] : Does IBIS describe output transition which both MOS turned on? D. C. Sessions
- RE: [SI-LIST] : Does IBIS describe output transition whic Muranyi, Arpad
- RE: [SI-LIST] : Does IBIS describe output transition whic Muranyi, Arpad
- RE: [SI-LIST] : Excessive clock overshoot Muranyi, Arpad
- [SI-LIST] : Re: Is feedback really EVIL? D. C. Sessions
- RE: [SI-LIST] : Excessive clock overshoot Andrew Ingraham
- Re: [SI-LIST] : Re: Is feedback really EVIL? Scott McMorrow
- Re: [SI-LIST] : Excessive clock overshoot] Dennis Tomlinson
- Re: [SI-LIST] : ANY EXPERIENCE OF MENTOR'S IS TOOLS Dennis Tomlinson
- RE: [SI-LIST] : Re: Is feedback really EVIL? Muranyi, Arpad
- Re: [SI-LIST] : Re: Is feedback really EVIL? D. C. Sessions
- [SI-LIST] : JOB POSTING Joachim Mueller
- RE: [SI-LIST] : Excessive clock overshoot Charles Hill
- [SI-LIST] : Transmission line model in Pspice Hamid Kharrati
- Re: [SI-LIST] : Excessive clock overshoot] Todd Westerhoff
- RE: [SI-LIST] : Transmission line model in Pspice Tan, Chun Chiat
- Re: [SI-LIST] : IBIS Version 3.0 Stephen Peters
- Re: [SI-LIST] : IBIS Version 3.0 Jon Powell
- [SI-LIST] : Si-List administrative trivia Ray Anderson
- [SI-LIST] : MECL information Colm Aengus Murphy
- Re: [SI-LIST] : MECL information Clyde R. Visser, KD6GWN
- [SI-LIST] : MECL book+ribbon cable Robert Wenzel
- RE: [SI-LIST] : MECL information Andrew Ingraham
- [SI-LIST] : Re: [SI-LIST] - MECL inform david
- Re: [SI-LIST] : IBIS Version 3.0 Gregory P. Fitzgerald
- [SI-LIST] : Contact Current Rating ? WonSae Sim
- [SI-LIST] : microwave radiation due to network analyzers Tan, Tat Hin
- [SI-LIST] : Re: microwave radiation due to network analyzers [email protected]
- [SI-LIST] : Re: microwave radiation due to network analyzers [email protected]
- [SI-LIST] : Re: microwave radiation due to network analyzers [email protected]
- Re: [SI-LIST] : Contact Current Rating ? Dennis Tomlinson
- Re: [SI-LIST] : Contact Current Rating ? Dennis Tomlinson
- FW: [SI-LIST] : Contact Current Rating ? Ellis, John R
- [SI-LIST] : si-list software modification Ray Anderson
- Re: [SI-LIST] : Contact Current Rating ? Patrick Lawler
- Re: [SI-LIST] : attenuation calculations Howard Johnson
- [SI-LIST] : Re: [old] Differential Reflection Question Howard Johnson
- [SI-LIST] : How to construct guard bands in Ansoft 2D Grasso, Charles
- [SI-LIST] : Signal Integrity position available Joe Cahill
- [SI-LIST] : Characteristic impedance Poulet P.
- [SI-LIST] : Another trace-Z question Peterson, James F
- Re: [SI-LIST] : Characteristic impedance [email protected]
- Re: [SI-LIST] : Characteristic impedance Joe Cahill
- Re: [SI-LIST] : Another trace-Z question Doug Brooks
- [SI-LIST] : How to construct guard bands in Ansoft 2D Grasso, Charles
- Re: [SI-LIST] : Characteristic impedance Dennis Tomlinson
- [SI-LIST] : EMC-98, 1 June, Santa Clara CA [email protected]
- [SI-LIST] : Re: EMC-98, 1 June, Santa Clara CA [email protected]
- Re: [SI-LIST] : How to construct guard bands in Ansoft 2D Eric Bogatin
- Re: [SI-LIST] : How to construct guard bands in Ansoft 2D J. Eric Bracken
- RE: [SI-LIST] : How to construct guard bands in Ansoft 2D Michael Tsuk
- RE: [SI-LIST] : How to construct guard bands in Ansoft 2D Eric Bogatin
- [SI-LIST] : method for identifying Xtalk and SSO noise ? Weber Chuang
- [SI-LIST] : Re: MEASURING POWER GROUND IMPEDANCE Istvan NOVAK
- [SI-LIST] : Dielectric Constant M. Susan Tweeton
- [SI-LIST] : Allowable crosstalk on VGA signals to monitor on PC ? McCormick, Robert
- [SI-LIST] : Allowable crosstalk on VGA signals to monitor on PC ? McCormick, Robert
- [SI-LIST] : Fwd:Allowable crosstalk on VGA signals to monito [email protected]
- [SI-LIST] : MECL Book Colm Aengus Murphy
- [SI-LIST] : AGP impedance compensated drivers? Andrew Ingraham
- [SI-LIST] : RE: AGP impedance compensated drivers? Andrew Ingraham
- Re: [SI-LIST] : Re: MEASURING POWER GROUND IMPEDANCE Howard Johnson
- [SI-LIST] : Definition for rise time? Weber Chuang
- Re: [SI-LIST] : Definition for rise time? Scott McMorrow
- [SI-LIST] : Diode Termination of Transmission Lines Peter Baxter
- Re: [SI-LIST] : Diode Termination of Transmission Lines [email protected]
- RE: [SI-LIST] : Diode Termination of Transmission Lines Peterson, James F
- Re: [SI-LIST] : Diode Termination of Transmission Lines Ron Wilhelmson
- RE: [SI-LIST] : AGP impedance compensated drivers? Volk, Andrew M
- Re: [SI-LIST] : Diode Termination of Transmission Lines Roland F. Portman
- Re: [SI-LIST] : Diode Termination of Transmission Lines Larry Smith
- [SI-LIST] : si-list archives Ray Anderson
- SI-LIST archives (was RE: [SI-LIST] : admin test message (ignore Andrew Ingraham
- Re: [SI-LIST] : Re: MEASURING POWER GROUND IMPEDANCE Istvan NOVAK
- [SI-LIST] : Dieletric Constant Polyimide Eric B. Lewis
- Re: [SI-LIST] : Dieletric Constant Polyimide Thomas Ngo
- RE: [SI-LIST] : Dieletric Constant Polyimide Andrew Ingraham
- Re: [SI-LIST] : Dieletric Constant Polyimide Nirmal Jain
- Re: [SI-LIST] : Dieletric Constant Polyimide Ray Anderson
- [SI-LIST] : Re: Fw: Spice models??? Stephen Peters
- Re: [SI-LIST] : High Permittivity Board Level Decoupling and related issues Elya B. Joffe
- Re: [SI-LIST] : High Permittivity Board Level Decoupling and related issues Larry Smith
- Re: [SI-LIST] : High Permittivity Board Level Decoupling and related issues Mark Randol
- Re: [SI-LIST] : High Permittivity Board Level Decoupling and [email protected]
- AW: [SI-LIST] : High Permittivity Board Level Decoupling and rela ted Neibig Uwe
- RE: [SI-LIST] : High Permittivity Board Level Decoupling and related issues Grasso, Charles
- Re: [SI-LIST] : High Permittivity Board Level Decoupling and Howard Johnson
- Re: [SI-LIST] : Re: MEASURING POWER GROUND IMPEDANCE Howard Johnson
- [SI-LIST] : Spice Mode for Emacs Randy Hamilton
- [SI-LIST] : Termination for bi-directional lines Poulet P.
- Re: [SI-LIST] : High Permittivity Board Level Decoupling and related issues Elya B. Joffe
- Re: [SI-LIST] : Termination for bi-directional lines Dennis Tomlinson
- Re: [SI-LIST] : Termination for bi-directional lines Poulet P.
- [SI-LIST] : Bus bar current carrying capability Kon, Hon Lee
- RE: [SI-LIST] : High Permittivity Board Level Decoupling and rela Andrew Ingraham
- [SI-LIST] : Bus bar current carrying capability Chandrakant Hemraj Sakharwade
- RE: [SI-LIST] : Bus bar current carrying capability Mackillop, William J.
- [SI-LIST] : Measuring Ground Noise Mark Nass
- RE: [SI-LIST] : Measuring Ground Noise Grasso, Charles
- Re: [SI-LIST] : Measuring Ground Noise Larry Smith
- Re: [SI-LIST] : Measuring Ground Noise Dima Smolyansky
- RE: [SI-LIST] : Measuring Ground Noise Andrew Ingraham
- [SI-LIST] : SI engineer available Joy Li
- Re: [SI-LIST] : Measuring Ground Noise John Fisher
- RE: [SI-LIST] : Measuring Ground Noise Larry Smith
- Re: [SI-LIST] : Measuring Ground Noise Mark Randol
- Re: [SI-LIST] : Measuring Ground Noise Istvan NOVAK
- Re: [SI-LIST] : Measuring Ground Noise Chris Rokusek
- [SI-LIST] : Terminations scheme for bi-directional bus M. Susan Tweeton
- Re: [SI-LIST] : Terminations scheme for bi-directional bus M. Susan Tweeton
- Re: [SI-LIST] : Terminations scheme for bi-directional bus Roland F. Portman
- [SI-LIST] : EDN SI tool Jay Diepenbrock
- Re: [SI-LIST] : Terminations scheme for bi-directional bus Dennis Tomlinson
- [SI-LIST] : Training course in SPICE Ravinder Ajmani
- Re: [SI-LIST] : Terminations scheme for bi-directional bus Scott McMorrow
- Re: [SI-LIST] : Terminations scheme for bi-directional bus M. Susan Tweeton
- RE: [SI-LIST] : Terminations scheme for bi-directional bus George Harris
- Re: [SI-LIST] : Terminations scheme for bi-directional bus Scott McMorrow
- Re: [SI-LIST] : Terminations scheme for bi-directional bus Dennis Tomlinson
- Re: [SI-LIST] : Terminations scheme for bi-directional bus Roy McCammon
- Re: [SI-LIST] : Training course in SPICE Syed Huq
- Re: [SI-LIST] : Terminations scheme for bi-directional bus Dennis Tomlinson
- [SI-LIST] : Dielectric withstand voltage requirements Jim Healy
- Re: [SI-LIST] : Terminations scheme for bi-directional bus Joe Cahill
- [SI-LIST] : Measuring PLL jitter Mark Nass
- RE: [SI-LIST] : Measuring PLL jitter Mellitz, Richard
- RE: [SI-LIST] : Measuring PLL jitter Zhang, Michael T
- [SI-LIST] : How substrate noise influence input levels..??? Yehuda D. Yizraeli
- [SI-LIST] : Standard Component Data Sheet Bob Davis
- RE: [SI-LIST] : Standard Component Data Sheet again Bob Davis
- Re: [SI-LIST] : Si-List administrative trivia Chris Rokusek
- [SI-LIST] : Re: FS: Book (numerical electromagnetics) Todd Nichols
- [SI-LIST] : Design Note on Right Angle Bends Mike Mayer
- Re: [SI-LIST] : Design Note on Right Angle Bends Gerald Johnson
- Re: [SI-LIST] : Design Note on Right Angle Bends Scott McMorrow
- [SI-LIST] : Re: [SI-LIST] - Design Note david
- Re: [SI-LIST] : Design Note on Right Angle Bends Nirmal Jain
- RE: [SI-LIST] : Design Note on Right Angle Bends Greg Edlund
- Re: [SI-LIST] : Design Note on Right Angle Bends Mark Randol
- [SI-LIST] : Split vs. common chip busses Mike Degerstrom
- [SI-LIST] : looking for "CMOS Simultaneous Switching Noise" Howard Johnson
- [SI-LIST] : Decomposing PCB elements for RF(ish) applications Mark McKee
- Re: [SI-LIST] : Design Note on Right Angle Bends [email protected]
- Re: [SI-LIST] : Design Note on Right Angle Bends Todd Westerhoff
- Re: [SI-LIST] : Design Note on Right Angle Bends Ronda Faries
- Re: [SI-LIST] : Design Note on Right Angle Bends Doug Brooks
- [SI-LIST] : IC DIE SHRINK Poulet P.
- Re: [SI-LIST] : IC DIE SHRINK Scott McMorrow
- Re: [SI-LIST] : IC DIE SHRINK Stephen Peters
- Re: [SI-LIST] : Design Note on Right Angle Bends [email protected]
- RE: [SI-LIST] : Design Note on Right Angle Bends Eric Bogatin
- Re: [SI-LIST] : Design Note on Right Angle Bends [email protected]
- Re: [SI-LIST] : Split vs. common chip busses Mike Degerstrom
- Re: [SI-LIST] : Split vs. common chip busses Mike Degerstrom
- [SI-LIST] : Crow bar current (dc switching current) vs power Elias Lozano
- Re: [SI-LIST] : Crow bar current (dc switching current) vs power Vinu Arumugham
- [SI-LIST] : Cross-talk Concerns Alex Theodorou
- Re: [SI-LIST] : Cross-talk Concerns Daniel Lake
- Re: [SI-LIST] : Cross-talk Concerns Prasad Modali - Katmai Design
- [SI-LIST] : Mixed signal - PWR and GND configuration issue Chris Roberts
- Re: [SI-LIST] : IC DIE SHRINK Purge
- Re: [SI-LIST] : Mixed signal - PWR and GND configuration issue John Fisher
- Re: [SI-LIST] : Mixed signal - PWR and GND configuration issue Roland F. Portman
- [SI-LIST] : Non-ideal return current paths [email protected]
- [SI-LIST] : Surface Mount Cap Lead Inductance Mike Mayer
- Re: [SI-LIST] : IC DIE SHRINK [email protected]
- [SI-LIST] : PCB design company Poulet P.
- [SI-LIST] : GND plane heat dissipation Tim Parks
- Re: [SI-LIST] : GND plane heat dissipation Mike Keenly
- RE: [SI-LIST] : GND plane heat dissipation Andrew Ingraham
- RE: [SI-LIST] : GND plane heat dissipation Tim Parks
- [SI-LIST] : [Fwd: (no subject)] Yeap Swee Cheong
- Re:RE: [SI-LIST] : GND plane heat dissipation [email protected]
- Re: [SI-LIST] : [Fwd: (no subject)] Mike Degerstrom
- [SI-LIST] : Expression for inductance of a flat conductor Salvador Aguinaga
- Re: [SI-LIST] : Expression for inductance of a flat conductor [email protected]
- [SI-LIST] : Switching Current in a high-speed digital pcb: How to calculate Salvador Aguinaga
- [SI-LIST] : Signal Integrity In General Van T. Hua
- [SI-LIST] : Power-Down effect on power supply voltage and Clocks Yehuda D. Yizraeli
- [SI-LIST] : Seeking T-Tech Quick-Circuit used equipment Howard Johnson
- [SI-LIST] : 3.3V Design Peterson, James F
- Re: [SI-LIST] : 3.3V Design Mike Mayer
- Re: [SI-LIST] : 3.3V Design Joe Cahill
- Re: [SI-LIST] : 3.3V Design Dennis Tomlinson
- Re: [SI-LIST] : 3.3V Design Dennis Tomlinson
- Re: [SI-LIST] : 3.3V Design M. Susan Tweeton
- Re: [SI-LIST] : 3.3V Design [email protected]
- Re: [SI-LIST] : 3.3V Design Dennis Tomlinson
- Re: [SI-LIST] : 3.3V Design M. Susan Tweeton
- Re: [SI-LIST] : 3.3V Design Ronen Sima
- Re: [SI-LIST] : Non-ideal return current paths Vigliarolo Roberto
- [SI-LIST] : Clock tree [email protected]
- RE: [SI-LIST] : Clock tree George Harris
- Re: [SI-LIST] : Clock tree Scott McMorrow
- RE: [SI-LIST] : Clock tree Mellitz, Richard
- Minimum or Maximum package for SI Worst Case simulation? John Lin - TAO
- [SI-LIST] : daisy chain [email protected]
- Re: [SI-LIST] : daisy chain Dennis Tomlinson
- Re: [SI-LIST] : Surface Mount Cap Lead Inductance Vigliarolo Roberto
- Re: [SI-LIST] : Surface Mount Cap Lead Inductance Ray Anderson
- Re: [SI-LIST] : Surface Mount Cap Lead Inductance Larry Smith
- Re: [SI-LIST] : Surface Mount Cap Lead Inductance Brett Grossman
- Re: [SI-LIST] : Surface Mount Cap Lead Inductance Larry Smith
- Re: [SI-LIST] : Surface Mount Cap Lead Inductance Dennis Tomlinson
- Re: [SI-LIST] : Surface Mount Cap Lead Inductance Mark Randol
- [SI-LIST] : Decoupling capacitors Poulet P.
- Re: [SI-LIST] : Surface Mount Cap Lead Inductance Ray Anderson
- Re: [SI-LIST] : Surface Mount Cap Lead Inductance [email protected]
- Re: [SI-LIST] : Decoupling capacitors Larry Smith
- Re: [SI-LIST] : Surface Mount Cap Lead Inductance Ray Anderson
- Re: [SI-LIST] : Surface Mount Cap Lead Inductance Mark Randol
- Re: [SI-LIST] : Decoupling capacitors [email protected]
- Re: [SI-LIST] : Surface Mount Cap Lead Inductance Vigliarolo Roberto
- Re: [SI-LIST] : Surface Mount Cap Lead Inductance Larry Smith
- Re: [SI-LIST] : Decoupling capacitors Ray Anderson
- [SI-LIST] : crosstalk through resistor networks? Andrew Phillips
- Re: [SI-LIST] : crosstalk through resistor networks? Dennis Tomlinson
- Re: [SI-LIST] : crosstalk through resistor networks? Joe Cahill
- RE: [SI-LIST] : 3.3V Design Andrew Ingraham
- RE: [SI-LIST] : Clock tree Andrew Ingraham
- RE: [SI-LIST] : 3.3V Design Tim Morley
- re: [SI-LIST] : crosstalk through resistor networks? fabrizio zanella
- Re: [SI-LIST] : Clock tree Vinu Arumugham
- Re: [SI-LIST] : crosstalk through resistor networks? Mark McKee
- RE: [SI-LIST] : Clock tree Andrew Ingraham
- [SI-LIST] : SI opening - EMC fabrizio zanella
- [SI-LIST] : High Speed Design method Papanna Manjunatha
- [SI-LIST] : Trace impedance casperdd
- RE: [SI-LIST] : Trace impedance John Philips
- [SI-LIST] : Fibre-Channel Equaization Circuits Doug Piper
- Re: [SI-LIST] : Trace impedance Bill Dempsey
- [SI-LIST] : Position Available, Doug Piper
- Re: [SI-LIST] : Fibre-Channel Equaization Circuits Jinhua Chen
- Re: [SI-LIST] : Trace impedance [email protected]
- Re: [SI-LIST] : Trace impedance Doug Brooks
- Re: [SI-LIST] : Trace impedance fabrizio zanella
- Re: [SI-LIST] : crosstalk through resistor networks? Jory McKinley
- Re: [SI-LIST] : Trace impedance Jim Lyke
- Re: [SI-LIST] : crosstalk through resistor networks? Dennis Tomlinson
- Re: [SI-LIST] : Trace impedance Dan Swanson
- Re: [SI-LIST] : crosstalk through resistor networks? Jory McKinley
- Re: [SI-LIST] : Trace impedance Dima Smolyansky
- Re: [SI-LIST] : Trace impedance Charles Bishop
- Re: [SI-LIST] : Trace impedance Jim Lyke
- [SI-LIST] : Re: Trace impedance [email protected]
- [SI-LIST] : Re: Trace impedance Juliusz Poltz
- FWD+: Re: [SI-LIST] : Trace impedance [email protected]
- FWD+: Re: [SI-LIST] : Trace impedance Dr. Edward P. Sayre
- [SI-LIST] : overshoot Jeff Miller-FJM039
- [SI-LIST] : TDR analysis casperdd
- Re: [SI-LIST] : overshoot Dennis Tomlinson
- Re: [SI-LIST] : TDR analysis Dima Smolyansky
- [SI-LIST] : timing design tool Poulet P.
- Re: [SI-LIST] : overshoot Joe Cahill
- RE: [SI-LIST] : timing design tool Bishop, Ron
- [SI-LIST] : Making trace impedance tolerance range Volk, Andrew M
- [SI-LIST] : Signal integrity simulation tool - your opinion and recommandation [email protected]
- [SI-LIST] : SI in cells. Savithri S.
- Re: [SI-LIST] : SI in cells. Chandrakant Hemraj Sakharwade
- RE: [SI-LIST] : Signal integrity simulation tool - your opinion a George Harris
- Re: [SI-LIST] : Signal integrity simulation tool - your opinion and recommandation M. Susan Tweeton
- Re: [SI-LIST] : Signal integrity simulation tool - your opinion a nd recommandation Fred Balistreri
- [SI-LIST] : SI models creation. [email protected]
- Re: [SI-LIST] : SI models creation. Stephen Peters
- [SI-LIST] : Priority of test pads Tim Parks
- [SI-LIST] : SI Models Creation [email protected]
- [SI-LIST] : Relative permeability of KOVAR Chris Cheng
- RE: [SI-LIST] : Trace impedance Chris Knapton
- [SI-LIST] : Crosstlak in ultra high speed pcb Yeap Swee Cheong
- [SI-LIST] : IBIS Model Verification Abe Riazi
- [SI-LIST] : models page on http://www.eia.org/eig/ibis/ibis.htm Chinh Tran
- Re: [SI-LIST] : IBIS Model Verification Weston Beal
- Re: [SI-LIST] : IBIS Model Verification Stephen Peters
- Re: [SI-LIST] : IBIS Model Verification (correction) Kellee Crisafulli
- Re: [SI-LIST] : IBIS Model Verification (correction) Ray Anderson
- [SI-LIST] : Power-plane resonance article Ray Anderson
- Re: [SI-LIST] : IBIS Model Verification (correction) Chris Rokusek
- Re: [SI-LIST] : Power-plane resonance article Heinz Blennemann
- Re: [SI-LIST] : Power-plane resonance article [email protected]
- FW: [SI-LIST] : IBIS Model Verification (correction) Greg Edlund
- Re: [SI-LIST] : Power-plane resonance article Mike Mayer
- Re: [SI-LIST] : models page on http://www.eia.org/eig/ibis/ibis.htm Jon Powell
- [SI-LIST] : SPICE Models P. Manjunatha
- [SI-LIST] : IBIS Model Verification Abe Riazi
- Re: [SI-LIST] : IBIS Model Verification Weston Beal
- [SI-LIST] : SPICE Models Jay Diepenbrock
- Re: [SI-LIST] : IBIS Model Verification John V Fitzpatrick
- Re: [SI-LIST] : IBIS Model Verification [email protected]
- [SI-LIST] : mpc68360 Motorola IBIS models Chinh Tran
- RE: [SI-LIST] : mpc68360 Motorola IBIS models Tieng Nguyen
- Re: [SI-LIST] : Power-plane resonance article Mike Mayer
- Re: [SI-LIST] : Power-plane resonance article Pat Zabinski
- Re: [SI-LIST] : Signal Integrity In General Tom Warneke
- [SI-LIST] : diode terminations(?) Fred Rosenberger
- RE: [SI-LIST] : IBIS Model Verification Abe Riazi
- Re: [SI-LIST] : diode terminations(?) axlchiu
- [SI-LIST] : New VME Backplane -- Star Layout Mike Mayer
- RE: [SI-LIST] : New VME Backplane -- Star Layout Peterson, James F
- Re: [SI-LIST] : New VME Backplane -- Star Layout Mike Mayer
- Re: [SI-LIST] : New VME Backplane -- Star Layout Bob Meyer
- [SI-LIST] : Miller Capacitance [email protected]
- [SI-LIST] : Complex Planes Eric B. Lewis
- re: [SI-LIST] : Complex Planes Eric B. Lewis
- Re: [SI-LIST] : Complex Planes danla
- RE: [SI-LIST] : Complex Planes Dima Smolyansky
- [SI-LIST] : Short Course - 2nd announcement Paul Franzon
- [SI-LIST] : Conducted EMC Testing of PLL jitter Ray Anderson
- Re: [SI-LIST] : Conducted EMC Testing of PLL jitter Pat Zabinski
- Re: [SI-LIST] : Conducted EMC Testing of PLL jitter [email protected]
- RE: [SI-LIST] : Conducted EMC Testing of PLL jitter Farrokh Mottahedin
- RE: [SI-LIST] : Conducted EMC Testing of PLL jitter Colin Brench
- Re: [SI-LIST] : Conducted EMC Testing of PLL jitter Fred Balistreri
- RE: [SI-LIST] : Conducted EMC Testing of PLL jitter Ray Anderson
- Re: [SI-LIST] : Conducted EMC Testing of PLL jitter [email protected]
- RE: [SI-LIST] : Conducted EMC Testing of PLL jitter [email protected]
- [SI-LIST] : need new BGA vendor Pat Zabinski
- RE: [SI-LIST] : Conducted EMC Testing of PLL jitter Zhang, Michael T
- Re: [SI-LIST] : Conducted EMC Testing of PLL jitter [email protected]
- [SI-LIST] : USB differential lines. Laurent BERNARD
- [SI-LIST] : USB differential lines. Laurent BERNARD
- [SI-LIST] : PCB design rules for Ultra 2 SCSI SE / LVD differential lines. Laurent BERNARD
- [SI-LIST] : PCB design rules for Ultra 2 SCSI SE / LVD differential lines. Laurent BERNARD
- RE: [SI-LIST] : Conducted EMC Testing of PLL jitter [email protected]
- Re: [SI-LIST] : need new BGA vendor Michael Freda
- Re: [SI-LIST] : USB differential lines. Norm Ebsary
- Re: [SI-LIST] : USB differential lines. Doug Brooks
- Re: [SI-LIST] : PCB design rules for Ultra 2 SCSI SE / LVD differential lines. Fred Balistreri
- Re: [SI-LIST] : USB differential lines. Fred Balistreri
- Re: [SI-LIST] : USB differential lines. Norm Ebsary
- RE: [SI-LIST] : Conducted EMC Testing of PLL jitter Charles Hill
- RE: [SI-LIST] : Conducted EMC Testing of PLL jitter Norman Wong
- [SI-LIST] : Jitter Measurement [email protected]
- Re: [SI-LIST] : Jitter Measurement Dima Smolyansky
- Re: [SI-LIST] : Conducted EMC Testing of PLL jitter yuan
- [SI-LIST] : BGA Ni-Au platting pattern. komerix
- Re: [SI-LIST] : BGA Ni-Au platting pattern. Gregory P. Fitzgerald
- Re: [SI-LIST] : BGA Ni-Au platting pattern. Brett Grossman
- Re: [SI-LIST] : BGA Ni-Au platting pattern. Fred Balistreri
- [SI-LIST] : Controlled Z PCB's Craig Clewell
- [SI-LIST] : Er vs T [email protected]
- [SI-LIST] : IBIS delay line model Dennis Tomlinson
- [SI-LIST] : Also, Er vs. freq. Chris Padilla
- SI Mailing List [email protected]
- [SI-LIST] : Also, Er vs. freq. Chris Padilla
- [SI-LIST] : IC input impedance [email protected]
- RE: [SI-LIST] : IC input impedance Dima Smolyansky
- [SI-LIST] : How to model chip to SDRAM pc board Yehuda D. Yizraeli
- RE: [SI-LIST] : IC input impedance Dima Smolyansky
- RE: [SI-LIST] : IC input impedance Andrew Ingraham
- Re: [SI-LIST] : IC input impedance Dima Smolyansky
- (Fwd) RE: [SI-LIST] : IC input impedance Pat Zabinski
- Re: [SI-LIST] : IC input impedance Fred Balistreri
- RE: [SI-LIST] : IC input impedance Chris Padilla
- Re: [SI-LIST] : IC input impedance Alok Tripathi
- RE: [SI-LIST] : IC input impedance Marin Sampaleanu
- Re: [SI-LIST] : IC input impedance Dennis Tomlinson
- Re: [SI-LIST] : IC input impedance Dennis Tomlinson
- Re: [SI-LIST] : IC input impedance Dima Smolyansky
- [SI-LIST] : 440BX IBIS model (help find) Kevin Chung
- Re: [SI-LIST] : 440BX IBIS model (help find) Scott McMorrow
- [SI-LIST] : A/D and D/A Converters PWR/GND Connection Elya B. Joffe
- [SI-LIST] : Selection of Optimum Termination Abe Riazi
- RE: [SI-LIST] : Selection of Optimum Termination Bob Davis
- RE: [SI-LIST] : A/D and D/A Converters PWR/GND Connection Peterson, James F
- [SI-LIST] : On-board Switching Power Supply Ravinder Ajmani
- Re: [SI-LIST] : Selection of Optimum Termination Poulet P.
- RE: [SI-LIST] : Selection of Optimum Termination Bob Davis
- [SI-LIST] : On-board Switching Power Supply Jay Diepenbrock
- [SI-LIST] : A/D and D/A Converters PWR/GND Connection Jay Diepenbrock
- RE: [SI-LIST] : Selection of Optimum Termination Abe Riazi
- RE: [SI-LIST] : Selection of Optimum Termination Abe Riazi
- [SI-LIST] : A/D and D/A Converters PWR/GND Connection Dr. Edward P. Sayre
- [SI-LIST] : Schottky diode termination Doug Brooks
- [SI-LIST] : UnNamed Dan Swanson
- [SI-LIST] : Differential Signals M. Susan Tweeton
- [SI-LIST] : Printed Circuit Design's 1999 Editorial Calendar Ronda Faries
- [SI-LIST] : RE: Freeware for demonstration of transmission line reflections Warren Sande
- [SI-LIST] : RE: (transmission line demo tool) Andrew Ingraham
- RE: [SI-LIST] : Differential Signals George Harris
- [SI-LIST] : D/A and A/D Connections Elya B. Joffe
- Re: [SI-LIST] : Differential Signals Mike Jenkins
- [SI-LIST] : RE: (transmission line demo tool) Dan Swanson
- [SI-LIST] : Re: [SI-LIST] (transmission line demo tool) Pat Zabinski
- Re: [SI-LIST] : D/A and A/D Connections Dennis Tomlinson
- [SI-LIST] : twisted pair attenuation [email protected]
- Re: [SI-LIST] : Differential Signals M. Susan Tweeton
- [SI-LIST] : Schottky diode termination John Philips
- [SI-LIST] : RE: Schottky diode termination Abe Riazi
- Re: [SI-LIST] : Schottky diode termination Dennis Tomlinson
- Re: [SI-LIST] : Schottky diode termination [email protected]
- RE: [SI-LIST] : Schottky diode termination Andrew Ingraham
- RE: [SI-LIST] : Schottky diode termination John Philips
- RE: [SI-LIST] : Schottky diode termination Andrew Ingraham
- RE: [SI-LIST] : Schottky diode termination Abe Riazi
- [SI-LIST] : Schottky diode termination Peterson, James F
- RE: [SI-LIST] : Schottky diode termination Peterson, James F
- [SI-LIST] : Schottky diode termination Fred Rosenberger
- [SI-LIST] : New Book: "Digital Systems Engineering" by Dally and Poulton Fred Rosenberger
- [SI-LIST] : positions Jon Powell
- Re: [SI-LIST] : Schottky diode termination Dennis Tomlinson
- RE: [SI-LIST] : Schottky diode termination Muranyi, Arpad
- RE: [SI-LIST] : Schottky diode termination Robert Muir
- Re: [SI-LIST] : Schottky diode termination Mike Monett
- RE: [SI-LIST] : Schottky diode termination [email protected]
- [SI-LIST] : EDE opportunities at Sun Mike Fleice [CONTRACTOR]
- [Fwd: [SI-LIST] : Schottky diode termination] Dennis Tomlinson
- RE: [SI-LIST] : Schottky diode termination Bob Davis
- RE: [SI-LIST] : Schottky diode termination Shenoy, Jay
- RE: [SI-LIST] : Schottky diode termination Muranyi, Arpad
- RE: [SI-LIST] : Schottky diode termination Bob Perlman
- RE: [SI-LIST] : Schottky diode termination Bob Davis
- [SI-LIST] : No subject given [email protected]
- RE: [SI-LIST] : No subject given West, Todd
- Re[2]: [SI-LIST] : USB & LVDS Differential signals routing [email protected]
- [SI-LIST] : High Speed Queries Lum Wee Mei
- RE: Re[2]: [SI-LIST] : USB & LVDS Differential signals routing West, Todd
- [SI-LIST] : 5v and 3.3v Poulet P.
- Re: [SI-LIST] : High Speed Queries Roland F. Portman
- Re: [SI-LIST] : High Speed Queries [email protected]
- Re: [SI-LIST] : High Speed Queries Fred Rosenberger
- Re: [SI-LIST] : High Speed Queries Syed Huq
- RE: [SI-LIST] : 5v and 3.3v Bob Davis
- RE: [SI-LIST] : High Speed Queries Bob Davis
- Re: [SI-LIST] : High Speed Queries Yehuda D. Yizraeli
- [SI-LIST] : Clock skew [email protected]
- Re: [SI-LIST] : Trace impedance C.C. Chiu
- RE: [SI-LIST] : High Speed Queries Bob Davis
- [SI-LIST] : Open position - Viewlogic Europe Cary Mandel
- [SI-LIST] : query Savithri
- Re: [SI-LIST] : Trace impedance Dennis Tomlinson
- Re: [SI-LIST] : Clock skew Weston Beal
- [SI-LIST] : Termination and Test Equipment leads Peter Baxter
- Re: [SI-LIST] : Termination and Test Equipment leads Craig Clewell
- Re: [SI-LIST] : Termination and Test Equipment leads [email protected]
- [SI-LIST] : Differential impedance fabrizio zanella
- Re: [SI-LIST] : Differential impedance Mike Jenkins
- Re: [SI-LIST] : Differential impedance Alok Tripathi
- Re: [SI-LIST] : Differential impedance J. Eric Bracken
- Re: [SI-LIST] : Differential impedance Danwei Xue
- RE: [SI-LIST] : Differential impedance Dima Smolyansky
- [SI-LIST] : RC terminations on multidrop busses Roy Leventhal
- Re: [SI-LIST] : Differential impedance Doug Brooks
- Re: [SI-LIST] : Differential impedance Danwei Xue
- [SI-LIST] : Simulating Tools Adrian Lynam
- Re: [SI-LIST] : Simulating Tools Chris H Simon
- Re: [SI-LIST] : Simulating Tools [email protected]
- [SI-LIST] : Re: DIFFERENTIAL ROUTING-- what to do? -- Salvador Aguinaga
- Re: [SI-LIST] : Simulating Tools [email protected]
- RE: [SI-LIST] : RC terminations on multidrop busses Abe Riazi
- Re: [SI-LIST] : query Savithri
- [SI-LIST] : RE: RC terminations on multidrop busses Roy Leventhal
- Re: [SI-LIST] : RE: RC terminations on multidrop busses Magnus Homann
- RE: [SI-LIST] : RE: RC terminations on multidrop busses Abe Riazi
- RE: [SI-LIST] : RE: RC terminations on multidrop busses Abe Riazi
- Re: [SI-LIST] : Simulating Tools [email protected]
- Re: [SI-LIST] : RE: RC terminations on multidrop busses Roy Leventhal
- Re: [SI-LIST] : Trace impedance Dennis Tomlinson
- RE: [SI-LIST] : RE: RC terminations on multidrop busses John Fisher
- [SI-LIST] : Fwd: Connector question on SI John Fisher
- RE: [SI-LIST] : RE: RC terminations on multidrop busses Bob Davis
- RE: [SI-LIST] : RE: RC terminations on multidrop busses Alok Tripathi
- [SI-LIST] : conductor thickness versus current Tim Parks
- Re: [SI-LIST] : Trace impedance Craig Clewell
- Re: [SI-LIST] : conductor thickness versus current Mike Dudinsky X3204
- [SI-LIST] : A timing question in high speed bus =?gb2312?B?wfXK97Hy?=
- RE: [SI-LIST] : A timing question in high speed bus Andrew Ingraham
- RE: [SI-LIST] : A timing question in high speed bus Muranyi, Arpad
- [SI-LIST] : =?iso-8859-1?Q?=BB=D8=B8=B4:_=5BSI-LIST=5D_:_A_timing_question_in_hig?= =?iso-8859-1?B?wfXK97Hy?=
- Re: [SI-LIST] : =?iso-8859-1?Q?=BB=D8=B8=B4?=: [SI-LIST] : A timing Scott McMorrow
- RE: [SI-LIST] : A timing question in high speed bus Scott McMorrow
- RE: [SI-LIST] : A timing question in high speed bus =?iso-8859-1?B?wfXK97Hy?=
- [SI-LIST] : RE: Models & EDA Vendors Dima Smolyansky
- RE: [SI-LIST] : A timing question in high speed bus Bob Davis
- [SI-LIST] : Substrate modeling R.S.Krishnan
- Re: [SI-LIST] : Substrate modeling Steve Corey
- Re: [SI-LIST] : Substrate modeling R.S.Krishnan
- Re: [SI-LIST] : Substrate modeling Xavier Aragones
- [SI-LIST] : Some issues about fineline BGA .. Andrew Phillips
- RE : [SI-LIST] : RE: Models & EDA Vendors Weber Chuang
- RE : RE : [SI-LIST] : RE: Models & EDA Vendors Weber Chuang
- [SI-LIST] : GTLP16612 Termination Kon, Hon Lee
- Re: RE : RE : [SI-LIST] : RE: Models & EDA Vendors [email protected]
- RE: RE : [SI-LIST] : RE: Models & EDA Vendors Dima Smolyansky
- [SI-LIST] : Focusing on Parasitic Parameters Abe Riazi
- Re: RE : RE : [SI-LIST] : RE: Models & EDA Vendors Jay Diepenbrock
- Re: [SI-LIST] : Some issues about fineline BGA .. Mike Degerstrom
- [SI-LIST] : TestPad R,L,C Bishop, Ron
- Re: [SI-LIST] : Focusing on Parasitic Parameters Mike Jenkins
- [SI-LIST] : RE: Dima Smolyansky
- RE : [SI-LIST] : RE: TDR modeling Weber Chuang
- RE: [SI-LIST] : Focusing on Parasitic Parameters Abe Riazi
- [SI-LIST] : Backplane connectors for Fibre Channel Grasso, Charles
- [SI-LIST] : Calculating Trace Inductance Douglas McKean
- Re: [SI-LIST] : Calculating Trace Inductance Danwei Xue
- Re: [SI-LIST] : Calculating Trace Inductance Douglas McKean
- RE: [SI-LIST] : Calculating Trace Inductance Eric Bogatin
- Re: [SI-LIST] : Calculating Trace Inductance Doug Brooks
- RE: [SI-LIST] : Backplane connectors for Fibre Channel Farrokh Mottahedin
- RE : [SI-LIST] : RE: TDR modeling Weber Chuang
- [SI-LIST] : Slew rate Chang_Ie_Hwaa
- Re: [SI-LIST] : Calculating Trace Inductance Craig Clewell
- Re: [SI-LIST] : Backplane connectors for Fibre Channel Craig Clewell
- RE: [SI-LIST] : Some issues about fineline BGA .. Andrew Ingraham
- RE: [SI-LIST] : Focusing on Parasitic Parameters Andrew Ingraham
- RE: [SI-LIST] : Focusing on Parasitic Parameters Abe Riazi
- Re: [SI-LIST] : Focusing on Parasitic Parameters Christian Schuster
- [SI-LIST] : MPI: Metalized Particle Interconnect Lai, Ricky
- [SI-LIST] : Career Opportunity Cohen, Fred
- Re: [SI-LIST] : Focusing on Parasitic Parameters Scott McMorrow
- Re: [SI-LIST] : Focusing on Parasitic Parameters and ISI Scott McMorrow
- RE: [SI-LIST] : Slew rate Muranyi, Arpad
- RE: [SI-LIST] : Conducted EMC Testing of PLL jitter Farrokh Mottahedin
- RE: [SI-LIST] : Conducted EMC Testing of PLL jitter Farrokh Mottahedin
- [SI-LIST] : JOB POSTING : Signal Integrity Engineer Ron Mosher
- [SI-LIST] : TDR Analysis: Layer Peeling Algorithm using Matlab Christian Schuster
- RE: [SI-LIST] : TDR Analysis: Layer Peeling Algorithm using Matlab Dima Smolyansky
- [SI-LIST] : SI University programs Richard Gaunt
- Re: [SI-LIST] : TDR Analysis: Layer Peeling Algorithm using Matlab Christian Schuster
- Re: [SI-LIST] : SI University programs [email protected]
- Re: [SI-LIST] : SI University programs Georg Ramsch
- [SI-LIST] : Re: Georg Ramsch
- Re: [SI-LIST] : SI University programs treytnar
- [SI-LIST] : SI University programs [email protected]
- [SI-LIST] : Text Book in SI alaa alani
- Re: [SI-LIST] : Text Book in SI Roy Leventhal
- Re: [SI-LIST] : Text Book in SI Chris Padilla
- RE: [SI-LIST] : Text Book in SI Heck, Howard
- Re: [SI-LIST] : Text Book in SI Douglas McKean
- [SI-LIST] : Signal Ground at the connector ycchien
- [SI-LIST] : Book on RF Package Modeling Dean Monthei TQO
- Re: [SI-LIST] : Signal Ground at the connector Roland F. Portman
- [SI-LIST] : Book on RF Package Modeling Dean Monthei TQO
- [SI-LIST] : Book on RF Package Modeling Dean Monthei TQO
- Re: [SI-LIST] : Signal Ground at the connector ycchien
- [SI-LIST] : CBT for Signal Integrity [email protected]
- [SI-LIST] : IBIS models Michael Werner
- [SI-LIST] : How to estimate total layers needed or trace pitch? [email protected]
- Re: [SI-LIST] : How to estimate total layers needed or trace pitch? Dennis Tomlinson
- Re: [SI-LIST] : How to estimate total layers needed or trace Douglas McKean
- [SI-LIST] : Transmission Line Theory Gary
- Re: [SI-LIST] : Transmission Line Theory Shreeram Siddhaye
- Re: [SI-LIST] : Transmission Line Theory Pat Zabinski
- RE: [SI-LIST] : Transmission Line Theory Heck, Howard
- Message from mail server (no name)
- Re: [SI-LIST] : Propagation velocity / discontinuous reference plane Larry Smith
- fwd: Re: [SI-LIST] : Does IBIS describe output transition which both Jean-Claude Perrin
- [SI-LIST] : Bus bar current carrying capability Kon, Hon Lee
Last message date: Sun 20 Jun 1999 - 03:56:60 PST
Archived on: Fri Mar 05 1999 - 14:11:25 PST
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