Re: [SI-LIST] : High Permittivity Board Level Decoupling and related issues

Larry Smith (ldsmith@lisboa.eng.sun.com)
Mon, 15 Jun 1998 12:58:10 -0700 (PDT)

Elya - some really good questions here. An eR (relative permittivity)
of 5000 for the dielectric between power planes is much larger than
numbers that I am aware of. This would give us substantial
capacitance with a small board area, but there is a down side. The
time of flight for electro-magnetics goes up as sqrt(eR). It will
take current 70 times longer to get from one side of a PCB to another
with the high eR material.

With normal FR4 material, any charge stored on a 6x6 inch square PCB
power planes is available within about 1 nSec (a typical rise time). The
high eR material will allow the power planes to hold much more charge,
but it may take 70 nSec to get to where it is needed! If an impulse
of current is required to satisfy an ASIC that is switching in 1 nSec,
it will have to come from an area that is about 0.1 inches away. Even
standard decoupling capacitor components mounted on these planes would
suffer the same time delay. The situation could be remedied by having
several pairs of power planes in parallel: some with high eR material
and some without. If a sufficient number of vias were used to connect
the planes, there would be charge on the high eR planes and it could
be bussed around on the fast planes.

700 nF is a pretty impressive amount of capacitance for power planes,
but it will not be enough to supply large currents at low frequencies.
Depending on the bandwidth of your regulator, you will need some amount
of bulk capacitance, even with the high eR power planes.

Concerning question (b), the concepts for decoupling analog circuits
should be the same as for digital: keep the power distribution
impedance as low as possible over a broad frequency range. Make
certain that the analog circuits can get at low impedance power at
the frequencies where the circuits will be drawing power.

regards,
Larry Smith
Sun Microsystems

------------- Begin Forwarded Message-------------

From: "Elya B. Joffe" <ebj@netvision.net.il>
To: SI-LIST@silab.eng.sun.com
Date: Mon, 15 Jun 1998 21:58:39 +2
MIME-Version: 1.0
Content-transfer-encoding: 7BIT
Subject: Re: [SI-LIST] : High Permittivity Board Level Decoupling and related
issues

Dear Members,

a) High Permittivity Dielectrics

We are considering to use, for RF and ultra-high speed digital
circuits, very high permittivity dielectrics between the PCBs ("Thick
Film FODEL").

Assume a separation between GND and VCC of 1.6mil, and a dielectric
constant Epsilon(r) of 5,000.

We have calculated that for a sq. Inch of PCB this is "worth" about
700nF of decoupling.

In this case, would discrete decoupling capacitors actually be
necessary, would they be of any avail or perhaps even the opposite?
Any input on this will be greatly appreciated.

b) Analog Circuit Decoupling

Does anyone know any "rule of thumb" for selecting the proper value of
decoupling capacitors for <underline>analog circuits</underline>? In
digital circuits - the rise time and switching currents of the devices
play an important role... What are the considerations in Analog
circuits???

Any reply to either or both questions will be greatly appreciated.

Thanks alot,

Elya B. Joffe - EMC Engineer

<nofill>
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