[SI-LIST] : EMC Issues with ASIC design

Manix Velu ([email protected])
Wed, 3 Dec 1997 18:15:27 +5:30


Can anyone help in identifying RFI emissions from our ASIC that runs
at 12MHz?

Our OEMs report that the emissions are from our ASIC only. The RFI is
coming at the n'th harmonics of the 12MHz. We are struggling to
suppress this by adding capacitors on the 12mA switching I/O pads of
the ASIC, reducing the loop-area covered by the external 12MHz
crystal circuitry, added a 47 ohms series resistor on the XTOUT pin
of the ASIC to the crystal, grounded the shields of the interface
connectors...and yet...there is no improvment.

Could any of you please throw some light on this issue? Is there any
thumb rules that we can follow to supress RFI for such end products?

Besides this, could any of you please advise, what are the EMC
fundamentals that we should consider while we deisgn the CMOS ASICs
that has the gate count of less than 12K and runs at 12 to 24MHz?

Thanks in Advance,

Manix Velu.

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