[SI-LIST] : Making trace impedance tolerance range

Volk, Andrew M (andrew.m.volk@intel.com)
Tue, 1 Sep 1998 09:58:00 -0700


Hello all -

I am looking for any opinions on the best known means of producing a
range of trace stack-ups that best represent the impedance range and
crosstalk one might encounter for a 10% or 15% tolerance board.
Typical microstrip traces of interest are 65 ohm nominal 6 mil trace
on 6.5 mil FR4 prepreg and 6 to 12 mil spacings; or 60 ohm nominal 5
mil trace on 4.5 mil FR4 prepreg with 15 to 20 mil spacings.

We have produced our own stack-ups in the past, but they are built on
our guesses of how the dielectric, trace width and height vary. I
suspect there are subtle differences (i.e. in cross capacitance and
inductance) for various stack-ups that might produce the same
"nominal" impedance. Asking the board vendors has been little help.
Either they are silent or give variations that when added up produce
tolerances well beyond the spec'ed value.

Is there any good way to produce a matrix of stack-ups (and attendant
L-C matrices to get at the realistic worst cases within the specified
manufacturing tolerance?

Regards,

Andrew Volk

-
************************************************************************
Andrew M. Volk E-mail: Andrew.M.Volk@intel.com
Principal Engineer
Graphics Components Division MS: FM5-64
Intel Corporation
1900 Prairie City Road Phone: (916) 356-5102
Folsom, CA 95630 FAX: (916) 356-3051
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