Re: component overstress

Arthur Collard (
Mon, 11 Mar 96 16:28:17 CST

Greg is correct about the power/ground pads toasted being a latchup
mechanism. The parasitic SCR is formed at the pin circuitry by the
CMOS layout. There are design rules to protect from this occuring
however the immunity vs. layout area tradeoff is of concern also. The
key here is that the pin is the entry point where the current flows
into the SCR to trigger the latch. This will occur when the product of
the parasitic NPN and PNP beta (open loop gain) is > or = 1. Latch-up
begins at one location and spreads drastically to several other
locations across die. Once the SCR is triggered the currents flow directly
from Power to Ground and cannot be stopped unless the chip is powered
down. By this time the chip has been overstressed and most likely damaged.
The damage occurs when the metal/silicon contact resistance drops (due
to aloying) to the point that the internal power metal evaporates (opens).
The SCR is a current triggered device so the assumption that several
drivers on on pin maybe correct but voltage overshoot must occur to foward
bias a pn junction.

Hope this helps



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