Re: [SI-LIST] : Decoupling capacitor selection & placement

D. C. Sessions (dc.sessions@tempe.vlsi.com)
Wed, 29 Oct 1997 08:09:20 -0700

Andrew Phillips wrote:

> When using decoupling capacitors to provide a low-impedance path between
> power and ground it appears to be well-established that we must do the
> following:
>
> - from device Vcc pin we drop a via to Vcc plane with as short a
> connection as possible (to minimize lead inductance). Same for device
> Gnd pin.
> - from capacitor pads we also drop vias to Vcc and Gnd planes with very
> short connections.
>
> What is the ruling for how close the capacitor needs to be to the device
> Vcc and Gnd pins?

Closer & shorter is better -- your design rules take over. On PWBs
with microvias and double-sided placement, it's actually possible to
share vias such that the device land has a via in it which surfaces
on the opposite side in the cap's land.

> For a device such as a microprocessor with multiple Vcc and Gnd pins,
> how do we determine how many capacitors will be required?
>
> Many references suggest that using 1 x 0.1 uF cap per Vcc-Gnd pair is a
> good rule-of-thumb - how is this value determined, and are there
> situations when it is invalid?

There's a diminishing-returns function here. After all, many devices
have a pair of power connections for every four I/Os -- and they have
32 or 64 I/Os in as little as 5 square cm. When your bypass caps take
more room than the part, it's time to give up.

-- 
D. C. Sessions
dc.sessions@tempe.vlsi.com