I have discovered in doing similar 400 Mhz simulations
with ps timing margins on a source synchronous bus, that
the big issue is usually Intersymbol Interference (ISI). Designers
that come at signal integrity from the communications theory
world are well aware of ISI on signal timing (jitter) behavior.
Designers that come at signal integrity from the digital design
world tend to forget, or not know, that we are working with
baseband signals that can have significant data dependent
DC offset shifts which will effect timing jitter.
At 400Mhz it is often the case that a waveform does not
have enough time to reach it's DC final value. This can be due
to an over driven signal that rings and has an edge rate faster than
necessary for the frequency of the bus. It can also be due to a
signal that has an edge rate which is not quite fast enough for
the frequency of the bus. In either case, there is significant
edge jitter due which is dependent upon the data pattern being
transmitted. For example, send a pattern of 7 zeros and
a one and then 7 zeros. Compare the crossings at the timing
measurement point with a pattern of 7 ones, a zero, and then
7 ones. There will be a difference. I guarantee that this is
usually an order of magnitude greater than the error in modeling
I don't mean to minimize the necessity for simulation vendors to
model via structures correctly. I have advocated this with my
simulaton vendor often. More voices crying in the wilderness
always help. However, to CAD vendors it is usually money that
speaks. Tie the request to a tangible market, or PO, and things
will often change quickly.
Abe Riazi wrote:
> Thanks for your reply.
> At the present time, there exists a noteworthy problem, in simulation
> field, associated with accurate modeling of vias.
> In my opinion, there is a real need for simulation programs to possess
> the capabiltiy to model both the via capacitance and inductance. For
> example, I was recently involved in a high frequency (400 MHz)
> simulation task of tight time margin (sub 100 ps). Practically, every
> picosecond was precious and had to be accounted for. There was a
> concern for simulation accuracy because the program we use (QUAD)
> ignores the parasitic via inductance.
> It seems to me that a PCB database plus other files (such as Global
> Control File), which are utilized by a simulation program, contain
> sufficient information to allow for modeling of via inductance.
> Included in these files are information related to substrate dielectric
> constant and thickness, number and types of layers (i.e. board stackup),
> trace geometries, topology of the nets, and via dimensions.
> Therefore, it is surprising (and undesirable) that simulation
> algorithms omit via inducatnce and model a via as a purely capacitive
> Abe Riazi,
> email: email@example.com
> >From: Andrew Ingraham[SMTP:Andrew.Ingraham@digital.com]
> >Sent: Sunday, November 29, 1998 8:26 PM
> >To: Abe Riazi
> >Cc: 'firstname.lastname@example.org'
> >Subject: RE: [SI-LIST] : Focusing on Parasitic Parameters
> >> ... Perhaps one conclusion implied by your
> >>email is following:
> >> It is simpler to quantify parasitic via capacitance than via
> >This is certainly true. It is easy to determine capacitance as a static
> >problem and typically it doesn't change much from its value at 0Hz.
> >Determining inductance, on the other hand, requires you to define a
> >closed loop. You will get different answers depending on how you choose
> >the loop that includes your via. The inductive effect of the via may be
> >imagined as being partly in series with the signal trace, partly in
> >series with its return path, since the return current may need to spread
> >out when reaching the via, to find enough capacitance to flow from one
> >plane to another. It's an interesting 3D problem that doesn't easily
> >shoe-horn into a simple 1D solution.
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-- ___________________________ Scott McMorrow Principal Engineer SiQual
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