I believe you can model packages and boards very accurately using TDR =
measurements. If you can deconvolve the true impedance profile from the =
TDR waveform, you can create a pretty good limited only by the incident =
rise time of your TDR instrument (which can be under 20ps). We have =
developed software that does exactly that - models the interconnects =
from TDR measurements, and verifies the model through integrated =
interface to a circuit simulator. We currently are SPICE based, but it =
is my understanding that there are very good SPICE to IBIS converters.
If you want more information, check out our web site or e-mail me.
TDA Systems, Inc.
7465 SW Elmwood St.
Portland, OR 97223
(503) 245-5684 (fax)
The Interconnect Modeling Company(tm)
From: Scott McMorrow [SMTP:email@example.com]
Sent: Wednesday, November 18, 1998 11:07 AM
To: Charles W. Martin
Cc: firstname.lastname@example.org; email@example.com
Subject: Re: Models & EDA Vendors
Generally, all models from component vendors, whether IBIS,
Quad, or Spice, should be considered suspect until used and
correlated against actual in-circuit operation. Oftentimes
models are not given the care that they deserve at the IC vendor.
They are often "extracted" by someone who doesn't understand
the problem. And the problem is multifold ....
Are the IV curves and waveform tables modeled accurately? If
care is taken, the accuracy of an IBIS model can correlate with
high precision to original HSPICE simulations or physical measurements.
If not, you might be in the right ballpark, you might not.
ICX/Zeelan models are based upon physical measurements, and so have
highly accurate characteristics. However, these are not worst case
measurements. They are based upon a sampling of typical
silicon. Care must be taken by the design engineer to insure that
worst case behavior is taken into account. However, in the absence
of manufacturer's models, these are the best you'll get ... and they
are very good. I use ICX/Zeelan models in my work when
manufacturer models are not available.
Are packages modeled correctly? In order to correctly model package
effects with high performance silicon devices with sub 500 ps
rise times, it is necessary to model the package in detail. This
usually requires a 3D field solver and results in numerous sections
of transmission line. Detailed package analysis by vendors is
rarely provided. Intel is an exception to this rule. There may be
other vendors which also provide this data in Ibis or Quad format, =
I am aware of few. It is generally next to impossible to get this data
from a manufacturer in any format, even Spice.
So are we totally out of the ballpark for most manufacturers? Well,
that depends. If you are concerned about tight timing margins
in the sub 500 ps range, then highly accurate model and package
characterization are absolutely necessary. You must work with
your chip suppliers to provide you accurate data. This often takes
multiple iterations to "help" them understand your problem.
Intel is an example of a vendor who has "generally" taken care in
characterizing their devices for worst case margin analysis.
However, if you are concerned about signal integrity effects alone,
(non-monotonicity, overshoot, undershoot, ringback, and crosstalk)
and their effect upon correct device operation and timing, and have
a bit of timing margin to spare, then the IBIS models which are
available from ICX/Zeelan, other independent model vendors, and
IC manufacturers will fit the bill. Using these models one can
perform very good board signal integrity analysis.
In my work, I use both options. I am often called upon to analyze
systems that have sub 500 ps and even sub 150 ps timing margins.
In these cases, I work closely with the manufacturers to obtain
IBIS and HSPICE device and package models. I often have to
perform my own HSPICE to IBIS conversions and correlations in order
to "know" that the data I am getting from simulations are accurate.
In other cases, I perform analysis on designs that are not pushing
the state of the art in performance, but are pushing the density
and complexity boundaries of a pc board. Here I am concerned about
noise, overshoot, undershoot, crosstalk and non-monotonicity
of asynchronous signals and clocks. I do complete board analysis
across worst case device corners. However, I usually have at least
1 ns or more of timing margins on most busses. In these cases
I have had incredible success with using manufacturer's, and
ICX/Zeelan based IBIS models. I still have to check them for
reasonableness, and I have to run them through IBIS parser
checks to ready them for my ICX simulation environments, but
these are minor nuisances compared to having no simulation
models at all.
I hope my comments have helped.
"Charles W. Martin" wrote:
> I've recently seen a demo for MGC's ICX tools (Including Tau for =
> verification). There software uses native IBIS models for timing and
> signal integrity estimations on the fly, and simulation.
> ICX mentions a library of 10K parts, as a first tier, afterwards there
> are two-tiers which cost the end-user progressively more for ICX to =
> ibis models.
> ICX mentions that they are working with ic vendors providing them with
> tools which would allow them to develop accurate ibis models =
> I'd like some feedback from anyone (ICX users, IC Vendors, etc..) who
> have worked with ICX on developing IBIS models.
> Secondly, we've found that many of the parts we'd like to simulate =
> don't exist in their library. While it's expected that newer =
> technologies might not have models, some of the models that are =
> are typical everyday parts/technologies. What's the preferred approach
> to obtaining and verifying accuracy of these parts?
> Lastly, IBIS is a great idea, and the people behind the scenes really
> deserve a round of applause. However, I'm interested in people's =
> on how widely available _accurate_ models are from component vendors.
> Thanks for your feedback,
> Charles Martin
> Cabletron Systems, Inc.
> EDA Tools
> Phone: (603) 337-2973
> Fax : (603) 337-1764
-- ___________________________ Scott McMorrow Principal Engineer SiQual
**** To unsubscribe from si-list: send e-mail to firstname.lastname@example.org. In the BODY of message put: UNSUBSCRIBE si-list, for more help, put HELP. si-list archives are accessible at http://www.qsl.net/wb6tpu/si-list ****