Intel has an opening for a Senior I/O Modeling Engineer. Basic job
Working with both the I/O buffer designers and board level simulation teams
to create and validate I/O buffer models for Intel's flagship microprocessors.
Planning and executing customer releases of both I/O buffer and package
Identifying Intel's future modeling needs (both I/O buffer and packaging)
and, by working with industry groups such as the IBIS Open Forum, ensure
that modeling solutions are made available to our customers.
The candidate must have a strong background in high speed board level
logic design, including transmission line analysis of PC board traces,
modeling of packages thru the use of field solver software, and use of
board level timing and signal integrity analysis tools. The candidate
must also poses strong analytical skills. Familiarity with Unix, HSPICE,
and some programming experience (PERL, C, etc.) is a definite plus. The
individual must be a self-starter, be self directed (comfortable working
with little or no direct supervision), and have a proven record of managing
small projects to completion. BSEE/CE or equivalent required.
Please direct all inquires/resumes to Stephen Peters at
firstname.lastname@example.org. You may also FAX your resume to (503) 264-4210.