[SI-LIST] : =?ISO-8859-1?Q?[SI-LIST]:_Premiere_course_on_=22Circuit_Simulation_and_Signal_Integrity=

Hartmut Grabinski ()
Wed, 25 Mar 1998 09:29:03 +0100

******************New Course********************

Circuit Simulation and Signal Integrity
Microelectronic Circuits and Systems

******************New Course********************

Detailed informations on

May 4-6, 1998
Holiday Inn SunSpree Resort
Scottsdale, Arizona

Course Objectives
This is the premiere course on signal integrity and computer support in
design and analysis of high-speed integrated circuits and systems. It is

taught by the leading European and US experts in the field with
extensive research and engineering experience in design of high-speed
high-performance microelectronic systems. The course objective is to
provide basic information on signal integrity and practical details on
suitable computer design tools, which are not covered in the literature
or user manuals. This knowledge is very important for successful designs

and efficient use of available tools. The lectures will be illustrated
by the examples taken from engineering practice in very successful
high-tech companies. Work stations will be available to participants for

hand-on experience with selected software tools.

Course Description
Signal integrity is a critical issue in designing contemporary
integrated circuits and systems which exhibit increasing speed and
complexity. Market forces and competition restrict design/development
time such that the use of sophisticated computer tools in design is
necessary. However, problems are so complex that full design automation
is not possible and these tools have many control parameters that have
to be user determined. Common example is the .OPTION list in the SPICE
type programs. Existing documentation provides limited assistance in
this matter. This practical course gives the fundamental knowledge
necessary to make the most efficient engineering decisions including
selection of necessary tools, development of design rules, and optimal
execution of design process. Attendees will have the opportunity to work

with advanced simulation programs.

This is a very practical course in high-speed, high-performance
integrated circuits and systems designed to accommodate attendees with
various backgrounds. Engineering examples will be used to illustrate the

problems and assist the listeners in absorbing the course material.
Applications of fundamentals will be stressed and maximum interaction
with the instructors and other participants will be encouraged. To aid
this interaction, it is suggested that participants prepare their
problems for discussion, consultation with lecturers, and simulation. No

specific software knowledge is required for computer
operations/exercises. Necessary instructions will be provided.

Who Should Attend

Digital logic designers
Circuit design engineers
System architects
CAD specialists
Packaging engineers
PCB layout professionals
Project and engineering managers
Application engineers

Advances in technology have resulted in standard integrated circuits
with rise times (switching edges) as short as 100 picoseconds. System
clock rates in excess of 200 MHz are common. Electrical designs become
very complex as they involve chip, package, printed circuit board
interconnections and signal transmission issues. Concurrently time
available to execute designs decreases requiring engineers and designers

to be very proficient in the skills and methods once only the province
of communication or supercomputer experts. Some of the "high-speed"
problems that engineers and system designers have to deal with are:
failures caused by the lack of control in interconnection impedance
(causing reflections and signal degradation), failures from interconnect

coupling, failures form signal degradation on the interconnect, failures

to meet electromagnetic interference (EMI) specifications. The course
will give participants the information to recognize problems and tools
to effectively deal with them. The instructors will draw from years of
their exposure to "high-speed" problems in research and industrial
environment of leading high-tech companies.

Registration will be held in the Foyer of the Holiday Inn Sunsspress
Resort Scottsdale, 7601 E. Indian Bend Road, Scottsdale, AZ 85250, on
Monday, May 4, 1998 from 7:00 to 8:00 a.m. The course fee of $1295
includes comprehensive course notes, refreshment breaks and 3 lunches.
If three or more people register from the same company, same work site,
the fee would be $995 each. The fee does not include lodging costs.
Register by mail, telephone, fax or e-mail using the attached form.
Early registration is encouraged as this course has limited space. The
University of Arizona reserves the right to cancel this course. In event

of cancellation all registration fees will be refunded in full. The
University of Arizona cannot be held responsible for costs incurred
other than the registration fee.

The Holiday Inn Sunspree Resort Scottsdale, 7601 E. Indian Bend Road,
Scottsdale, AZ 85250, phone 602-991-2400 or 1-800-364-9145 is holding a
block of rooms for participants, single or double occupancy, at $95.00
plus 10.725% tax. A deposit of one nights room and tax or credit card
guarantee must be received with your reservation. Should you cancel
within 72 hours of arrival or be a no show, this deposit will be
forfeited. Reservations must be made by April 3, 1998 in order to
guarantee this rate. After this date reservations will be accepted on a
space available basis only. Be sure to mention that you are attending
the CIRCUIT SIMULATION short course.

The Holiday Inn Sunspree Resort Scottsdale has arranged transportation
to and from their facility via the Super Shuttle at the Phoenix Airport
for $12.00 each way.

Participants will be awarded 2.0 Continuing Education Units (CEU) upon
completion of this course.

Contact the Office of Engineering Professional Development, The
University of Arizona, 1224 N. Vine Avenue, Tucson, Arizona 85719-4552,
phone 520-621-3054/5104, FAX 520-621-1443, e-mail: epd@engr.arizona.edu

Day 1
O. A. Palusinski, University of Arizona

Basis digital circuits attributes
Signal distribution
- delay, cross-talk, reflections
- driver-line-receiver interaction
Power and ground distribution
- switching noise (SN)
- techniques for containing SN
Circuit simulation
- SPICE, accuracy, convergence problems and remedies
guidelines for selection of control options
multiple simulation runs (SPICE in a loop).

Discussion: attendees input, open problems.

H. Grabinski, University of Hannover

Electromagnetic foundations
- wave propagation
- dispersion
- coupling and signal reflections
- circuit representations
- numerical simulation
- effects of conducting substrates.

Discussion: attendees input, open problems.


Day 2

H. Grabinski, University of Hannover

Time-domain simulation of coupled interconnecting lines
- efficient numerical simulation techniques
- interconnection with non-linear terminations
- expansion to multiple interconnections
Computer implementation of optimal simulation methods
- simulator ELDO
- basic ELDO properties
- use of ELDO (guidelines)
- examples of application
- computer practice/exercises in simulation

Discussion: attendees input, open problems.

R. Wenzel, Motorola, Inc.

Basics of ECL circuitry, ECL development: MECL to LVPECL
Transmission line models for high-speed logic
Termination methods for ECL
Handling fan out:
passive line splitting techniques
active buffered splitting
Fixed-frequency and 50% duty cycle lines
ECL clock distribution
System design issues
Clock frequency and data rate doubling, multiplication techniques
PC board layout for GHz ECL circuits:
power distribution and decoupling
signal routing and impedance control
Estimation of board and packaging effects on system performance
Low-voltage (3.3 V) LVECL and LVPECL
Basic ECL circuit and system modeling, SPICE modeling/simulation

Discussion: attendees input, open problems

Day 3

A. Muranyi, Intel Corp.

Effective use of simulators (SPICE in a loop, automation), examples:

parameter sweep
displaying of results
useful plotting tools
Signal transmission in CMOS technology, power/speed tradeoffs:
incident versus reflected wave switching
parallel versus series termination,
use of clamping diodes
Design of CMOS drivers and receivers
I-V transfer characteristics (DC)
V-t curves (transient characteristics)
Buffer load relations
load and buffer I-V characteristic
Bergeron diagram
lumped and distributed capacitive loading
effects of even/odd mode switching
Modeling of I/O buffers
effects of parasitic MOSFET diodes
modeling the connections external to power rails
effects of imperfections in clamping diodes
behavioral versus transistor level modeling
Signal integrity issues in low power, low voltage designs
advantages: faster operation, less power dissipation
problems: device leakage, reduced noise margins
clamping diodes and ring-back, need for differential inputs

Discussion: attendees input, open problems

O. A. Palusinski, University of Arizona

Switch capacitor circuits - simplest mixed-mode operation
Signal handling in switch capacitor circuits
Field programmable analog arrays (FPAA)
Programming support for FPAA

Discussion: trends in tool development, attendees input.


Hartmut Grabinski was born in Hildesheim, Federal Republic of Germany.
He received the Ing.(grad.) degree from the Fachhochschule Hannover in
1977 and the Dipl.-Ing. degree as well as the Dr.-Ing. degree and the
Dr.-Ing. habil. degree in 1982, 1987 and 1993, respectively, from the
University of Hannover, Germany. Presently Dr. Grabinski is the Manager
of the division of Design & Test in the Laboratory for Information
Technology, University of Hannover. In addition he is holding lectures
on "Electrical Performance of Electronic Packaging" and "Relativistic
Electrodynamics". His research interests are in the field of electronic
packaging and electrodynamics. He has developed novel, efficient methods

for computer simulation of interconnections. His results are implemented

in the commercial SPICE-like simulator ELDO distributed by

Arpad Muranyi, a native of Hungary, began his professional career as a
musician. However, his interests included electronics since the early
childhood. When he came to the United States in 1982 to continue his
education, he had the opportunity to learn more about electronics and
computers. In 1990 he began his formal education in Electronic
Engineering and graduated in May 1994 with a BSEE degree at California
State University Sacramento. He has been employed by Intel Corporation
in Folsom, CA since 1991 as a hardware systems engineer. His primary
assignments revolve around system level signal integrity simulations of
interconnects, I/O buffer modeling, specification and verification. The
I/O Buffer Information Specification (IBIS) modeling standard originated

from his work.

Olgierd A. Palusinski, is a Professor on the Department of Electrical
and Computer Engineering at the University of Arizona, where he teaches
and conducts research in integrated circuits and electronic packaging.
He is a Director of Circuit Simulation Laboratory at the University of
Arizona. He joined the University of Arizona in 1976. Prior to that he
was an Associate Professor of Electrical Engineering at the University
of Silesia, Poland. He spent his sabbaticals and several summers at
Motorola carrying research on electrical design of packages, integrated
circuit simulation, and field programmable analog arrays. He also
conducted research on computer aided design of electronic circuits,
packages and interconnections in German and French Universities. He was
a recipient of prestigious fellowships of German Science Foundation. Dr.

Palusinski obtained his M.Sc. and Ph.D. degrees in Electrical
Engineering from the Technical University of Silesia. He also studied in

France, where he received the Degree "Docteur de l'Universite de Lille".

He is a senior member of IEEE.

Robert J. Wenzel, received the BSEE and MSEE degrees from the University

of South Florida and the Ph.D. in Electrical Engineering from Georgia
Institute of Technology. His university research focused on the
development of multigigahertz digital ATE pin electronics using high
speed ECL and microwave system interconnect design techniques. His
experience includes several years of designing high performance ECL
system boards for gigabit-per-second test applications. He is currently
a Staff Engineer doing research on packaging and interconnect signal
integrity modeling for the System Interconnect Technology division of
Motorola's Advanced Interconnect Systems Laboratories. He is presently
working on analysis and design methodologies for high signal-count
digital and RF packages through the use of microwave theory and
full-wave electromagnetic solution.

Circuit Simulation and Signal Integrity Enrollment Application
Name _________________________________________________________________
Address ________________________________________________________________

(include Mail Stop)
City ___________________________ State _____ Zip ___________
Phone: ________________ Fax: ______________Email:_______________________

Registration Fee (Per Person)
Regular . . . . . . . . . . . . . . . . . . . $1295
Three or more - same work site. . $ 995
Please make checks payable to: The University of Arizona Foundation
Note: Registration fees are not a tax deductible contribution. However,
they may be deducted as a business expense. Check with your accountant
or tax advisor.
If you wish to use your VISA or MASTERCARD for registration:
Card # _________________________________________ Exp. Date __________
Signature ___________________________________________ Date __________
The University of Arizona accepts American Express Credit Card:
Card # _________________________________________ Exp. Date __________
Signature ___________________________________________ Date __________
(For Continuing Education Units, CEU)
SSN: _______________________________________________ DOB: ___________
Persons with a disability may request a reasonable accommodation, such
as a sign language interpreter, by contacting Engineering Professional
Development, 520-621-3054. Requests should be made as early as possible
to allow time to arrange the accommodation. I have the following special


Mail/Fax or e-mail this form to:
Engineering Professional Development
The University of Arizona
1224 N. Vine Avenue
Tucson, AZ 85719-4552 E-mail: epd@engr.arizona.edu
Website: http://intermix.engr.arizona.edu/~epd/#CSSI


hgra@lfi.uni-hannover.de Priv.-Doz. Dr. habil. Hartmut Grabinski
Laboratorium fuer Informationstechnologie
Universitaet Hannover
Schneiderberg 32 _/_/ _/_/_/_/ _/_/
Tel.: +49.511.762.5030 D-30167 Hannover _/_/ _/_/ _/_/
Fax : +49.511.762.5051 Germany _/_/ _/_/_/ _/_/
_/_/_/_/ _/_/ _/_/