RE: [SI-LIST] : Modeling Package parasitics

Charles Hill (chuckh@csn.net)
Sat, 28 Mar 1998 22:05:40 -0700

DC,

I found your comments interesting. I disagree on one point: a very low ESR
at an input. I have measured the ESR of device inputs. Different devices
have different ESRs, of course, and the ESR is typically frequency
dependent and DC bias dependent. The equivalent input resistance that I've
measured is typically between 10 and 100 ohms in the 10 to 100MHz range.
This shouldn't be surprizing considering the input has finite power gain
transistors. A very low input ESR means the device has a very high power
gain.

It would be interesting to measure the ESR on the power pins. I think in
terms of parallel equivalents since there are many structures in parallel.
I suspect there will be a significant shunt conductance and susceptance at
high frequencies as you allude to---all those transistor drains in
parallel. It should also be highly dependent on the loading on the output
I/O cells.

Charles Hill, consultant
Alta Engineering, chuckh@altaeng.com

----------
From: D. C. Sessions[SMTP:dc.sessions@tempe.vlsi.com]
Reply To: si-list@silab.Eng.Sun.COM
Sent: Wednesday, February 18, 1998 5:24 PM
To: si-list@silab.Eng.Sun.COM
Subject: Re: [SI-LIST] : Modeling Package parasitics

Howard Johnson wrote:
>
> Hello D.C.,
>
> What about the ESR of a chip's parasitic input capacitance? We had
> a big discussion about that in the gigabit ethernet group about
> a year ago, and nobody really ever came up with a
> satisfactory answer. Is it .1, 1, 10, or 100 ohms?

Hope I'm not shocking anyone with this answer, but:
It depends.

There are several components to Cchip.

First there's the pad itself. Bonding pads are generally pretty
large chunks of metal (80 microns square for 500nm processes is
common). This is over field oxide and P-bulk material, so it
tends to have a fairly high ESR -- without calculating, at least
hundreds of ohms.

Then there's the drain capacitance of outputs and bidirectional
cells. This one tends to be somewhat variable, depending on the
Rdson of the predriver since the dominant capacitance is the
gate-to-drain capacitance of the OFF transistors. This is commonly
5x or so of the Rdson of the driver itself, maybe 60-120 ohms each
for pullup and pulldown. In parallel is the drain-to-well capacitance,
which tends to have hundreds of ohms of ESR.

If the signal is input-only then it needs a separate ESD device
(on outputs the driver transistors do the job). Some designers
use hard grounds on the gates of these parts, giving very low ESRs
on the order of ohms. Others use resistors or turned-on transistors
and can have kohms.

At this point the input path runs into a protection resistor
(a hundred ohms or so) and can generally be treated as complete.

Bottom line: I'd SWAG the Cchip as two parts: about half with an
ESR of a kilohm, and half with an ESR of about 50 ohms. Those
who want a better answer than a guess from an I/O designer who's
spent the day on lawyerese should have a ago at lab measurements.

> At 04:13 PM 2/16/98 -0700, you wrote:
> >Mark Nass wrote:
> >>
> >> Does anybody have an accurate way of modeling package parasitics,
> >> in particular in a QUAD simulation environment. I have been using
> >> a lumped inductance for a BGA & SQFP package but find this to be very
> >> inaccurate with fast edge rates and small voltage level swings. The
ringing
> >> from the inductor causes the signal to cross switching thresholds in
the
> >> simulation environment, but this ringing is not seen on the lab bench.
> >> My feeling is that a specified ZO, TPD & and Length should be used
> >> for the bonding wire, trace on the BGA package and the pin.
> >> Does anybody have any thoughts on what values I could use for
> >> the bonding wire?
> >
> >Bondwires are actually very good inductors. The package itself
> >may be a PWB in implementation (consider BGAs). A good figure
> >for bondwire inductance is 40uH/in.
> >
> >One of the reasons that many simulations show excessive ringing
> >on ICs is that the capacitors are too high-Q. Most semiconductor
> >capacitances (such as the ESD structures on I/O circuits) have
> >quite large ESRs. Your best bet would be to correlate the ESR
> >to the lab data.

--
D. C. Sessions
dc.sessions@tempe.vlsi.com

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