Re: [SI-LIST] : How to identify SSO
D. C. Sessions (email@example.com)
Wed, 07 Jan 1998 13:54:11 -0700
Andrew Ingraham wrote:
> > Upon further reflection of Praveen's question on SSO, and all of the
> > responses, it seems like we are talking about two different things. Both
> > of which drive the VSS/VDD pin count.
> > One is overlap - which is defined as the time that both FETs in a
> > totem-pole output stage are turned on. As you all know, this has a
> > profound effect on a chip's dynamic current demand.
> > The other one is SSO (simultaneous switching outputs) - which I would
> > describe as the number of outputs - outputs that go off chip - that
> > simultaneously go high (or low) and draw (or source) extra current to
> > charge (or discharge) the load capacitance they see. Of course, this
> > can seriously impact the amount of ground bounce and power supply droop
> > a chip will see.
> > So, do they add? Not necessarily, if the design is a synchronous one and
> > the overlap is small. But if, as some of the e-mail states, the overlap
> > gets up to 10 ns, then there would be a cumulative effect.
> Not everyone is using "overlap" the same way. I think some used
> "overlap" to mean "multiple outputs that switch nearly simultaneously,
> such that their di/dt's overlap one another."
> I can't imagine that the overlap current of a single buffer (according
> to your first definition above) would approach 10 ns in any modern
> CMOS design.
10 ns? If one of mine exceeded 100 ps, I'd find another line of work.
Our usual constraint is that the crowbar charge can't exceed the
total charge required to switch the driver's intrinsic capacitance.
IMSNHO, NO well-designed driver has enough crowbar current to
bother about. It'd better be in the noise.
D. C. Sessions