Dear SI-land,
I'm pondering the wiring of some >1Ghz differential ECL, with
wire lengths reaching perhaps 10 inches. It has become clear
that this wiring could save alot of length (and other torture)
if vias were used, at least one and possibly two (per side).
These would be signal routing vias, not pin-escapes neatly
located near a discontinuity to a package.
Should I be concerned about the performance of these vias?
Anecdotal history tells me to expect a loading of perhaps 1pF
each, which I would not expect to be an issue. If each side
of the pair passes through a via at approximately the same
point in time, will the issue take care of itself?
Alternatively, is there a simply way to manage the "hit" these
vias will produce, perhaps by specific geometries or proximity
to reference (gnd)? I can envision quite a 3-d solver excer-
size attempting to use pad sizes versus planes versus clear-
ances etc.
Thanks in advance, from an electrically challenged layout
guy.
--Jeff Seeger Applied CAD Knowledge Inc Chief Technical Officer Tyngsboro, MA 01879 [email protected] 508 649 9800