RE: Re[2]: [SI-LIST] : Decoupling capacitor selection & plac

Dr. Edward P. Sayre (esayre@nesa.com)
Fri, 07 Nov 1997 12:13:38 -0500

Mr. Peterson:

The 100pF/sq.in matches the estimate. However, the planes of logic cards
can be well perforated by the anti-pads which give clearance for vias,
often as much as 50 - 60% of the plane is removed and the capcitance will
be reduced proportionately. In factthe capacitance could be substantially
less due to the fringing nature of the fields.

The people (Zycon/Hadco) who make the inner capacitance layers use a
substantially thinner capacitance layer (~2mils I think) which, although
subject to capcitance reduction, maintains a field distribution less
dependent on fringing reductions purely by virtue of the geometry.

I would count on numbers more like 25-35pF/sq.in in actuality for your
situation and resonable anti-pad sizes.

ed sayre

At 09:35 AM 11/6/97 -0500, you wrote:
>Ravinder,
>I am interested in your power plane capacitance analysis. Apparently
>you've done some tests in this area. Empirical data is always good.
>Could you give me the details of how you tested and what type of numbers
>you got from your measurements.
>I am considering straying from a dual stripline approach in my stackup
>to put a +5 and gnd next to each other. The reason was to add some high
>freq. capacitance to the board. Text books have stated that a pwr and
>gnd plane separated by 10 mils of FR-4 have a capacitance of 100 pF/sq
>inch. Does that match what you saw in your tests?
>If not, I might reconsider my approach...
>Thanks in advance for the info,
>Jim Peterson
>jfpeterson@space.honeywell.com
>
>> ----------
>> From: Ravinder Ajmani[SMTP:ajmani@us.ibm.com]
>> Sent: Friday, October 31, 1997 11:50 AM
>> To: si-list@silab.Eng.Sun.COM
>> Subject: Re: Re[2]: [SI-LIST] : Decoupling capacitor selection &
>> plac
>>
>> I have been studying the effects of increased power/ground capacitance
>> on noise
>> and EMI, and also to determine if I can use this option to reduce the
>> number of
>> capacitors on the board. I have used FR4 with thickness of 3 mils,
>> and also
>> Zycon material, which is 2 mils thick but is still FR4, and hence
>> doesn't
>> provide enough capacitance to make any significant difference. I have
>> inquired
>> with our raw card fabricators and none could provide me any details
>> about high
>> dielectric constant material.
>> I will be interested in using the EmCap material in my experiment. I
>> will
>> appreciate if Todd can inform me who in California has the capability
>> to
>> fabricate boards with this material.
>>
>> Regards, Ravinder
>> EMC & Signal Integrity Engineer
>> PCB Development and Design Department
>> Voice : (408) 256-7956 T/L : 276-7956 Fax : (408)
>> 256-0550
>> Email: ajmani@us.ibm.com
>>
>>
>> owner-si-list@silab.Eng.Sun.COM
>> 10/29/97 05:11 AM
>> Please respond to owner-si-list@silab.Eng.Sun.COM @ internet
>>
>> To:
>> cc: si-list@silab.Eng.Sun.COM @ internet
>> Subject: Re[2]: [SI-LIST] : Decoupling capacitor selection & placemen
>>
>> How does everyone feel about power/ground distributed
>> capacitance?
>>
>> Zycon originally developed ZBC2000 - a thin FR4 (.002")
>> power/ground
>> core with a capacitance of ~500pf/sq in (usually 2 cores are
>> used) -
>> as a decoupling capacitor replacement or adjunct.
>>
>> HADCO and Polyclad have developed EmCap - a 0.004" Ceramic / FR4
>> epoxy
>> power/ground core with 2750pf/sq in - as the next generation.
>>
>> I have been doing work to predict the ability of both these
>> products
>> to replace discrete capacitors in our customers boards and would
>> like
>> to hear some honest thoughts and feedback.
>>
>> FYI - I'm an EE working at HADCO. I work with the electrical
>> issues in
>> PWB - impedance, capacitance, layout, etc. - more or less in
>> house SI.
>>
>> Thanks!
>> Todd DeRego
>>
>>
>>
>>
>>
>>
>
>

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