The problem with die shrinks is that 'faster propagation delay'
really translates into faster *response* time of the IC. In other words,
after a die shrink an IC will respond to those 100mV/100ps input
pulses (usually due to crosstalk, mistermination, etc.) that it
formally rejected. Unfortunately, problems of this sort are usually
SI related and hard to fix after the fact.
To answer your question directly, it has been my experience that
the effects of a die shrink really depend on how good (i.e. noise free)
the board design is.
> My company once had a design working for several years until they shrank
> the die of a CPLD. Since then we had been experiencing sporadic failures
> and crashes until we found a solution. ( Terminating a few critical
> input signals ). So far not much new.
> My question is does any body know what could be the effects of a die
> shrink ( besides time delay and rise/fall time) on a component like a
> CPLD 2000 gates. I compared timing delays and rise time between the two
> processes and there were ( as claimed by the manufacturer ) almost the
> I could never get any clear answer from the manufacturer.
> Philippe Poulet
> RICOH Corp