I have been following this subject with great interest. I find it
and some times amusing to see the various opinions about clamping and ESD=
circuits, because there seems to be a certain amount of mystery around th=
However, figuring out how clamping works is not all that difficult if one
about it in terms of I-V curves and reflection (Bergeron) diagrams and/or=
voltage dividers. After all, the I-V curve of a diode (or ESD circuit) i=
similar to the I-V curve of a resistor, except that half of it is missing.
other words, clamping diodes look very much like a half sided resistor
an open within the normal operating region of the signal swing, but as a=20
resistor a diode drop outside the supply rails (if its there, that is).
Let's take a falling edge, for example. (I will use nice numbers to make=
simple). The buffer drives from 5 to 0 volts, with a 10 Ohm impedance in=
Ohm line. The ledge voltage at the output of the buffer will be +1 volt.
the line is unterminated at the end, the reflection will cause an undersh=
-3 volts (doubling the 4 volt step down from 5 volts). On the other hand=
there is a diode at the end of the line with a slope of 10 Ohms and a kne=
voltage at -1 volt, the original -3 volt open ended reflection voltage wi=
divided by the transmission line impedance and the diode resistance to -1=
-1V (diode knee voltage)
\ 10 Ohms (diode resistance)
|--o (clamped undershoot voltage)
\ 40 Ohms (transmission line impedance)
-3V (unterminated undershoot voltage)
There is nothing magic about this, and this calculation can be carried ou=
each round trip of reflection (if one has enough time to do it by hand). =
course, these results are only good for DC approximations, because the AC=
effects of the diode, such as turn on time, charge storage, etc. are not=20
accounted for. So it is still better to simulate the circuit, but the ab=
discussion helps in understanding what the clamps really do.
To answer some of the questions below, I would like to draw your attentio=
some of the well known specs. The PCI and the 100 MHz SDRAM spec, for
describes minimum required clamping currents (I-V curves) for the inputs.
are there for a reason, i.e. they are needed for "termination" purposes.
The newer specs of some IC manufacturers also describe the amount of
allowed on the input. This is usually done in the form of voltage and ti=
For example, you can exceed a certain voltage only for a certain amount o=
Unfortunately these effects are very difficult to spec, and some of these
are not too clear either.
However, this is an indication that the IC manufacturer knows that there
overshoot, and they know that if these overshoots exceed the limits the
may be damaged. (This may not always be the real reason for the spec,
Some times it could be just simply signal integrity related, if there is =
much overshoot, there will be too much ringback also, which may violate t=
threshold voltage limitations).
I hope this helped to shed some light on the subject. Sincerely,
Andrew Ingraham wrote:
> I first saw Schottky diode termination described in a rather old
> Fairchild ECL book. Diode termination was not often used for ECL,
> perhaps because the normal ECL parallel termination usually worked quit=
> well if you could afford the power dissipation.
> The TTL logic families had clamp diodes in their input structures, and=20
> one of their intended functions actually was to provide some amount of=20
> diode termination. This is one of the reasons why TTL was easy to work=
> with, sometimes even when the wires got long compared to the falltimes.=
> Many people who have used TTL do not realize that they have been making=
> use of diode termination all along.
> Most CMOS families also have input clamp diodes, and again they
> generally work as both input protection and partial signal termination.
Andrew, John, list,
It has long been my belief that the input clamp diodes on CMOS are for
the purpose of providing ESD protection, and for clamping the "occasional=
over/undershoot. They are not provided for the purpose of providing line=20
termination. My belief is based on verbal communiqu=E9 with cohorts and=20
apps. engineers (which is to say, it could be based on legend and=20
As a crude example, suppose a full 5V transition is launched onto an=20
electrically long 50 Ohm line, causing the propagation of a 100 mA=20
current wave. With no other termination or loads, and assuming a clamp=20
forward bias of about 1V, this would require the clamp diode to conduct=20
a peak current of about 80 mA. If this were a highly repetitive signal,=20
the duty cycle for each diode could approach 50%. I would expect serious=20
MTBF issues with this scenario. I would also expect the semiconductor
types on this list to shudder at the thought of such an abusive applicati=
(aside from the strong possibility that the circuit may not function
I would like to pose some related questions for anyone on the list - most=
particularly the semiconductor types:
1. Do the semiconductor companies ascribe and/or acquiesce to the use of
input clamp diodes for line termination?
2. What are typical limits for "one time" peak currents?
3. What are typical limits for repetitive peak currents?
4. What if I were to change the example above such that the driver launch=
3.5 volt wave (70 mA)? The clamp current would then peak at roughly 20
5. And finally, what if the line length were shorter, so that the clamp
duty cycle were only a few percent?
> Those CMOS devices without input diodes tend to be SI nightmares.=20
> In a multi-drop bus configuration, diode terminators may be needed at=20
> several places, perhaps as many as one per input. For a daisy-chain=20
> route, they may only be needed at the two ends. The best way to tell=20
> what works is to try, preferably in simulation with GOOD models.
> Andy Ingraham
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