Re: vias in ECL @ >1Ghz

Don Abernathey (dla@pyramid.com)
Tue, 1 Apr 1997 11:47:06 -0800

The interface you are laying out is usually point to point and the
vias are likely clustered at the end points (number depends on
termination type).

We can't ignore the effect of vias on a differential interface since
the reflections they cause are "seen" and not "rejected" by the
differential receiver. Vias aren't very long electrically, but if you
get enough of them in a trace, the effective impedance of the trace
will drop noticeably.

You really can't avoid vias in a standard multilayer PCB. You need two
per trace just to pin-escape a part. I suspect that you'll end up with
4 more when you hook up the terminations. Either hand-route or
severely constrain the autorouter to do what you would do if
hand-routing.

Just a note, if the customer is trying to drive a cable with this
differential interface, worry about loss (turning the signal into heat
- more signal making it to the cable means longer cable). Depends on
trace length and application of course, but long 4mil traces on 1/2oz
copper can lose an appreciable amount of the signal. Trade-off plane
spacing and perhaps overall board thickness for wide (e.g 10mil)
traces at the correct impedance.

There is a paper "The effects of vias on PCB traces", by the folks at
UltraCad Design, Inc. that you might find interesting. Try
'http://www.eskimo.com/~ultra/tech.htm' and download the pdf.

*************************
Thank you |
Don Abernathey |
(503)690-6234 |
dla@pyramid.com |
*************************

On Mar 31, 6:09pm, Jeff Seeger wrote:
> Subject: vias in ECL @ >1Ghz
> Dear SI-land,
>
> I'm pondering the wiring of some >1Ghz differential ECL, with
> wire lengths reaching perhaps 10 inches. It has become clear
> that this wiring could save alot of length (and other torture)
> if vias were used, at least one and possibly two (per side).
> These would be signal routing vias, not pin-escapes neatly
> located near a discontinuity to a package.
>
> Should I be concerned about the performance of these vias?
> Anecdotal history tells me to expect a loading of perhaps 1pF
> each, which I would not expect to be an issue. If each side
> of the pair passes through a via at approximately the same
> point in time, will the issue take care of itself?
>
> Alternatively, is there a simply way to manage the "hit" these
> vias will produce, perhaps by specific geometries or proximity
> to reference (gnd)? I can envision quite a 3-d solver excer-
> size attempting to use pad sizes versus planes versus clear-
> ances etc.
>
> Thanks in advance, from an electrically challenged layout
> guy.
> --
>
> Jeff Seeger Applied CAD Knowledge Inc
> Chief Technical Officer Tyngsboro, MA 01879
> jseeger@appliedcad.com 508 649 9800
>-- End of excerpt from Jeff Seeger