Intel Corporation has the following SI job opportunity available at our
newly built DuPont, Washington facility. DuPont is located between
Olympia and Tacoma on Interstate 5 near the Fort Lewis Army Base. DuPont
is approximately 50 miles south of Seatle.
Please reference "XTG IO Buffer Engineer" on all correspondence,
particularly on your resume. E-mail your ASCII text resume to both
Norris Palmanteer, Intel HR, at Norris_Palmanteer@ccm.dp.intel.com and
John Zavertnik, hiring manager, at firstname.lastname@example.org.
Position Title: I/O Buffer Model Engineer
Location: DuPont, WA
Hiring Manager: John Zavertnik
Responsible for producing, validating and supporting IBIS format I/O
buffer models for Intel's current and next generation microprocessors
and chipsets. The successful candidate will work closely with multi-site
organizations to assure IO model integrity across a variety of
development groups and platforms. In addition, the successful candidate
will be responsible for anticipating Intel's future needs in I/O buffer
modeling, and developing solutions through industry forums such as the
IBIS open Forum.
The position requires a BS/MSEE with 2-4+ years experience in hardware
design and CAD simulation environment. Knowledge of transmission lines
and signal integrity simulation tools such as Quad design and SPICE
required. Knowledge of IBIS highly desirable. The candidate should have
strong analytical skills. Good communication skills, a team player
attitude and the ability to work with various functional groups across
divisions are essential. Script programming experience such as Perl or
TCL is a definite plus. Some travel is required.
Intel Corporation is an equal opportunity employer and fully supports
affirmative action practices. Intel also supports a drug free workplace
and requires that all offers of employment be contingent on satisfactory
preemployment drug test results.
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Subject: SI job opportunity in Intel Santa Clara
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