Upon further reflection of Praveen's question on SSO, and all of the
responses, it seems like we are talking about two different things. Both
of which drive the VSS/VDD pin count.
One is overlap - which is defined as the time that both FETs in a
totem-pole output stage are turned on. As you all know, this has a
profound effect on a chip's dynamic current demand.
The other one is SSO (simultaneous switching outputs) - which I would
describe as the number of outputs - outputs that go off chip - that
simultaneously go high (or low) and draw (or source) extra current to
charge (or discharge) the load capacitance they see. Of course, this
can seriously impact the amount of ground bounce and power supply droop
a chip will see.
So, do they add? Not necessarily, if the design is a synchronous one and
the overlap is small. But if, as some of the e-mail states, the overlap
gets up to 10 ns, then there would be a cumulative effect.
happy new year,
> > From si-list-approval@silab.Eng.Sun.COM Fri Dec 19 23:15:02 1997
> > X-From: uucp Fri Dec 19 15:13 PST 1997
> > >Received: from mars.Sun.COM (mars.Sun.COM [126.96.36.199]) by
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> > (8.6.12/IDA-1.6); Fri, 19 Dec 1997 11:31:22 -0800
> > Date: Fri, 19 Dec 1997 10:50:28 -0800
> > From: email@example.com (Praveen G Shekokar)
> > To: si-list@silab.Eng.Sun.COM
> > Subject: [SI-LIST] : SSO : How to identify SSO groups?
> > Sender: owner-si-list@silab.Eng.Sun.COM
> > Content-Length: 1126
> > We are using our foundaries SSO rules to calculate number of VDD/VSS
> > pins required for our ASIC. Before we can use the SSO rules we need
> > identify signals that form a SSO group. The conventional technique I
> > of is to group signals of similar functionality into a SSO group
> > Address/Data bus.
> > In practice we have noticed that not all the signals of such a group
> > identical delays. Further they may not have identical output loads.
> > delays implies that not all the outputs switch at the same. E.g.
> > Let output1 switch at time T and output2 at time T+t1. If t1 is
small then the
> > switching current for output1, say I1, will overlap with switching
> > for output2, say I2, leading to overall increase in the switching
> > But if t1 is more than the time required for I1 to reduce to 0 then
> > overall switching current is going to be limited to max of I1 and
> > I want to know whether there are any guide lines for value of t1
> > can use to decide whether a signal is part of a SSO group.
> > Value of t1 is also required in designing address/data stepping.
> > thanks,
> > - Praveen Shekokar
Honeywell, Space Systems Division, M/S 934-5
13350 US 19 N., Clearwater, FL, 34624